;buildInfoPackage: chisel3, version: 3.1-SNAPSHOT, scalaVersion: 2.11.7, sbtVersion: 0.13.11, builtAtString: 2016-11-26 18:48:38.030, builtAtMillis: 1480186118030
circuit FFTUnpacked : 
  extmodule BBFSubtract : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFSubtract_1 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFSubtract_2 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFSubtract_3 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFSubtract_4 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFSubtract_5 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFSubtract_6 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFMultiply : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFMultiply_1 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFSubtract_7 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFAdd : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFMultiply_2 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFMultiply_3 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFAdd_1 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_2 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_3 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFSubtract_8 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFSubtract_9 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFAdd_4 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_5 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFMultiply_4 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFMultiply_5 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFSubtract_10 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFAdd_6 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFMultiply_6 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFMultiply_7 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFAdd_7 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_8 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_9 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFSubtract_11 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFSubtract_12 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFAdd_10 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_11 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFMultiply_8 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFMultiply_9 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFSubtract_13 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFAdd_12 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFMultiply_10 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFMultiply_11 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFAdd_13 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_14 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_15 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFSubtract_14 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFSubtract_15 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFAdd_16 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_17 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFMultiply_12 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFMultiply_13 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFSubtract_16 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFAdd_18 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFMultiply_14 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFMultiply_15 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFAdd_19 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_20 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_21 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFSubtract_17 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFSubtract_18 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFAdd_22 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_23 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFMultiply_16 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFMultiply_17 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFSubtract_19 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFAdd_24 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFMultiply_18 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFMultiply_19 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFAdd_25 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_26 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_27 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFSubtract_20 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFSubtract_21 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFAdd_28 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_29 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFMultiply_20 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFMultiply_21 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFSubtract_22 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFAdd_30 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFMultiply_22 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFMultiply_23 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFAdd_31 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_32 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_33 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFSubtract_23 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFSubtract_24 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFAdd_34 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_35 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFMultiply_24 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFMultiply_25 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFSubtract_25 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFAdd_36 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFMultiply_26 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFMultiply_27 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFAdd_37 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_38 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_39 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFSubtract_26 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFSubtract_27 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFAdd_40 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_41 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFMultiply_28 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFMultiply_29 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFSubtract_28 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFAdd_42 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFMultiply_30 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFMultiply_31 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFAdd_43 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_44 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_45 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFSubtract_29 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFSubtract_30 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFAdd_46 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_47 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFMultiply_32 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFMultiply_33 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFSubtract_31 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFAdd_48 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFMultiply_34 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFMultiply_35 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFAdd_49 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_50 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_51 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFSubtract_32 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFSubtract_33 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFAdd_52 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_53 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFMultiply_36 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFMultiply_37 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFSubtract_34 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFAdd_54 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFMultiply_38 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFMultiply_39 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFAdd_55 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_56 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_57 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFSubtract_35 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFSubtract_36 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFAdd_58 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_59 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFMultiply_40 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFMultiply_41 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFSubtract_37 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFAdd_60 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFMultiply_42 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFMultiply_43 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFAdd_61 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_62 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_63 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFSubtract_38 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFSubtract_39 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFAdd_64 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_65 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFMultiply_44 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFMultiply_45 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFSubtract_40 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFAdd_66 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFMultiply_46 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFMultiply_47 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFAdd_67 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_68 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_69 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFSubtract_41 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFSubtract_42 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFAdd_70 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_71 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  module DirectFFT : 
    input clock : Clock
    input reset : UInt<1>
    output io : {flip in : {valid : UInt<1>, bits : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[8], sync : UInt<1>}, out : {valid : UInt<1>, bits : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[8], sync : UInt<1>}}
    
    io is invalid
    io is invalid
    wire _T_5 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_5 is invalid @[DspReal.scala 165:19]
    _T_5.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_12 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_12 is invalid @[DspReal.scala 165:19]
    _T_12.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_316 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_316 is invalid @[DspReal.scala 165:19]
    _T_316.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_323 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_323 is invalid @[DspReal.scala 165:19]
    _T_323.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    node _T_624 = and(io.in.sync, io.in.valid) @[FFT.scala 32:66]
    reg sync : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 15:29]
    when io.in.valid : @[Counter.scala 59:17]
      node _T_627 = eq(sync, UInt<1>("h01")) @[Counter.scala 23:24]
      node _T_629 = add(sync, UInt<1>("h01")) @[Counter.scala 24:22]
      node _T_630 = tail(_T_629, 1) @[Counter.scala 24:22]
      sync <= _T_630 @[Counter.scala 24:13]
      skip @[Counter.scala 59:17]
    node _T_631 = and(io.in.valid, _T_627) @[Counter.scala 60:20]
    when _T_624 : @[CounterWithReset.scala 11:31]
      sync <= UInt<1>("h00") @[CounterWithReset.scala 11:38]
      skip @[CounterWithReset.scala 11:31]
    cmem _T_635 : UInt<1>[2] @[FFTUtilities.scala 169:21]
    reg _T_637 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 15:29]
    when io.in.valid : @[Counter.scala 59:17]
      node _T_639 = eq(_T_637, UInt<1>("h01")) @[Counter.scala 23:24]
      node _T_641 = add(_T_637, UInt<1>("h01")) @[Counter.scala 24:22]
      node _T_642 = tail(_T_641, 1) @[Counter.scala 24:22]
      _T_637 <= _T_642 @[Counter.scala 24:13]
      skip @[Counter.scala 59:17]
    node _T_643 = and(io.in.valid, _T_639) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_644 = _T_635[_T_637], clock
      _T_644 <= io.in.sync @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_645 = _T_635[_T_637], clock
    io.out.sync <= _T_645 @[FFT.scala 33:15]
    io.out.valid <= io.in.valid @[FFT.scala 34:16]
    wire _T_649 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_649 is invalid @[DspReal.scala 165:19]
    _T_649.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_656 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_656 is invalid @[DspReal.scala 165:19]
    _T_656.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire twiddle_rom : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[4] @[FFT.scala 39:25]
    twiddle_rom is invalid @[FFT.scala 39:25]
    wire _T_733 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_733 is invalid @[DspReal.scala 165:19]
    _T_733.node <= UInt<64>("h03ff0000000000000") @[DspReal.scala 166:14]
    wire _T_740 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_740 is invalid @[DspReal.scala 165:19]
    _T_740.node <= UInt<64>("h08000000000000000") @[DspReal.scala 166:14]
    wire _T_757 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_757 is invalid @[DspComplex.scala 14:22]
    _T_757.real.node <= _T_733.node @[DspComplex.scala 15:17]
    _T_757.imaginary.node <= _T_740.node @[DspComplex.scala 16:22]
    twiddle_rom[0].imaginary.node <= _T_757.imaginary.node @[FFT.scala 40:69]
    twiddle_rom[0].real.node <= _T_757.real.node @[FFT.scala 40:69]
    wire _T_761 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_761 is invalid @[DspReal.scala 165:19]
    _T_761.node <= UInt<64>("h03fed906bcf328d46") @[DspReal.scala 166:14]
    wire _T_768 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_768 is invalid @[DspReal.scala 165:19]
    _T_768.node <= UInt<64>("h0bfd87de2a6aea963") @[DspReal.scala 166:14]
    wire _T_785 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_785 is invalid @[DspComplex.scala 14:22]
    _T_785.real.node <= _T_761.node @[DspComplex.scala 15:17]
    _T_785.imaginary.node <= _T_768.node @[DspComplex.scala 16:22]
    twiddle_rom[1].imaginary.node <= _T_785.imaginary.node @[FFT.scala 40:69]
    twiddle_rom[1].real.node <= _T_785.real.node @[FFT.scala 40:69]
    wire _T_789 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_789 is invalid @[DspReal.scala 165:19]
    _T_789.node <= UInt<64>("h03fe6a09e667f3bcd") @[DspReal.scala 166:14]
    wire _T_796 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_796 is invalid @[DspReal.scala 165:19]
    _T_796.node <= UInt<64>("h0bfe6a09e667f3bcc") @[DspReal.scala 166:14]
    wire _T_813 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_813 is invalid @[DspComplex.scala 14:22]
    _T_813.real.node <= _T_789.node @[DspComplex.scala 15:17]
    _T_813.imaginary.node <= _T_796.node @[DspComplex.scala 16:22]
    twiddle_rom[2].imaginary.node <= _T_813.imaginary.node @[FFT.scala 40:69]
    twiddle_rom[2].real.node <= _T_813.real.node @[FFT.scala 40:69]
    wire _T_817 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_817 is invalid @[DspReal.scala 165:19]
    _T_817.node <= UInt<64>("h03fd87de2a6aea964") @[DspReal.scala 166:14]
    wire _T_824 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_824 is invalid @[DspReal.scala 165:19]
    _T_824.node <= UInt<64>("h0bfed906bcf328d46") @[DspReal.scala 166:14]
    wire _T_841 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_841 is invalid @[DspComplex.scala 14:22]
    _T_841.real.node <= _T_817.node @[DspComplex.scala 15:17]
    _T_841.imaginary.node <= _T_824.node @[DspComplex.scala 16:22]
    twiddle_rom[3].imaginary.node <= _T_841.imaginary.node @[FFT.scala 40:69]
    twiddle_rom[3].real.node <= _T_841.real.node @[FFT.scala 40:69]
    wire indices_rom : UInt<3>[14] @[FFT.scala 41:24]
    indices_rom is invalid @[FFT.scala 41:24]
    indices_rom[0] <= UInt<1>("h00") @[FFT.scala 41:24]
    indices_rom[1] <= UInt<1>("h00") @[FFT.scala 41:24]
    indices_rom[2] <= UInt<1>("h00") @[FFT.scala 41:24]
    indices_rom[3] <= UInt<3>("h04") @[FFT.scala 41:24]
    indices_rom[4] <= UInt<3>("h04") @[FFT.scala 41:24]
    indices_rom[5] <= UInt<2>("h02") @[FFT.scala 41:24]
    indices_rom[6] <= UInt<3>("h06") @[FFT.scala 41:24]
    indices_rom[7] <= UInt<3>("h04") @[FFT.scala 41:24]
    indices_rom[8] <= UInt<2>("h02") @[FFT.scala 41:24]
    indices_rom[9] <= UInt<1>("h01") @[FFT.scala 41:24]
    indices_rom[10] <= UInt<3>("h05") @[FFT.scala 41:24]
    indices_rom[11] <= UInt<3>("h06") @[FFT.scala 41:24]
    indices_rom[12] <= UInt<2>("h03") @[FFT.scala 41:24]
    indices_rom[13] <= UInt<3>("h07") @[FFT.scala 41:24]
    node start = mul(sync, UInt<3>("h07")) @[FFT.scala 43:19]
    wire _T_893 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_893 is invalid @[DspReal.scala 165:19]
    _T_893.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_900 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_900 is invalid @[DspReal.scala 165:19]
    _T_900.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_917 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 44:42]
    _T_917 is invalid @[FFT.scala 44:42]
    wire _T_921 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_921 is invalid @[DspReal.scala 165:19]
    _T_921.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_928 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_928 is invalid @[DspReal.scala 165:19]
    _T_928.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_945 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 44:42]
    _T_945 is invalid @[FFT.scala 44:42]
    wire _T_949 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_949 is invalid @[DspReal.scala 165:19]
    _T_949.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_956 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_956 is invalid @[DspReal.scala 165:19]
    _T_956.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_973 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 44:42]
    _T_973 is invalid @[FFT.scala 44:42]
    wire _T_977 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_977 is invalid @[DspReal.scala 165:19]
    _T_977.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_984 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_984 is invalid @[DspReal.scala 165:19]
    _T_984.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1001 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 44:42]
    _T_1001 is invalid @[FFT.scala 44:42]
    wire _T_1005 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1005 is invalid @[DspReal.scala 165:19]
    _T_1005.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1012 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1012 is invalid @[DspReal.scala 165:19]
    _T_1012.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1029 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 44:42]
    _T_1029 is invalid @[FFT.scala 44:42]
    wire _T_1033 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1033 is invalid @[DspReal.scala 165:19]
    _T_1033.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1040 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1040 is invalid @[DspReal.scala 165:19]
    _T_1040.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1057 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 44:42]
    _T_1057 is invalid @[FFT.scala 44:42]
    wire _T_1061 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1061 is invalid @[DspReal.scala 165:19]
    _T_1061.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1068 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1068 is invalid @[DspReal.scala 165:19]
    _T_1068.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1085 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 44:42]
    _T_1085 is invalid @[FFT.scala 44:42]
    wire twiddle : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[7] @[FFT.scala 44:37]
    twiddle is invalid @[FFT.scala 44:37]
    twiddle[0].imaginary.node <= _T_917.imaginary.node @[FFT.scala 44:37]
    twiddle[0].real.node <= _T_917.real.node @[FFT.scala 44:37]
    twiddle[1].imaginary.node <= _T_945.imaginary.node @[FFT.scala 44:37]
    twiddle[1].real.node <= _T_945.real.node @[FFT.scala 44:37]
    twiddle[2].imaginary.node <= _T_973.imaginary.node @[FFT.scala 44:37]
    twiddle[2].real.node <= _T_973.real.node @[FFT.scala 44:37]
    twiddle[3].imaginary.node <= _T_1001.imaginary.node @[FFT.scala 44:37]
    twiddle[3].real.node <= _T_1001.real.node @[FFT.scala 44:37]
    twiddle[4].imaginary.node <= _T_1029.imaginary.node @[FFT.scala 44:37]
    twiddle[4].real.node <= _T_1029.real.node @[FFT.scala 44:37]
    twiddle[5].imaginary.node <= _T_1057.imaginary.node @[FFT.scala 44:37]
    twiddle[5].real.node <= _T_1057.real.node @[FFT.scala 44:37]
    twiddle[6].imaginary.node <= _T_1085.imaginary.node @[FFT.scala 44:37]
    twiddle[6].real.node <= _T_1085.real.node @[FFT.scala 44:37]
    node _T_1298 = add(start, UInt<1>("h00")) @[FFT.scala 49:67]
    node _T_1299 = tail(_T_1298, 1) @[FFT.scala 49:67]
    node _T_1301 = bits(indices_rom[_T_1299], 2, 2) @[FFT.scala 49:76]
    node _T_1303 = add(start, UInt<1>("h00")) @[FFT.scala 49:150]
    node _T_1304 = tail(_T_1303, 1) @[FFT.scala 49:150]
    node _T_1306 = bits(indices_rom[_T_1304], 1, 0) @[FFT.scala 49:159]
    wire _T_1316 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1316 is invalid @[DspReal.scala 165:19]
    _T_1316.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_43 of BBFSubtract @[DspReal.scala 102:36]
    BBFSubtract_43.out is invalid
    BBFSubtract_43.in2 is invalid
    BBFSubtract_43.in1 is invalid
    BBFSubtract_43.in1 <= _T_1316.node @[DspReal.scala 81:21]
    BBFSubtract_43.in2 <= twiddle_rom[_T_1306].real.node @[DspReal.scala 82:21]
    wire _T_1323 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_1323 is invalid @[DspReal.scala 83:19]
    _T_1323.node <= BBFSubtract_43.out @[DspReal.scala 84:14]
    wire _T_1339 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_1339 is invalid @[DspComplex.scala 14:22]
    _T_1339.real.node <= twiddle_rom[_T_1306].imaginary.node @[DspComplex.scala 15:17]
    _T_1339.imaginary.node <= _T_1323.node @[DspComplex.scala 16:22]
    node _T_1341 = add(start, UInt<1>("h00")) @[FFT.scala 49:219]
    node _T_1342 = tail(_T_1341, 1) @[FFT.scala 49:219]
    node _T_1350 = bits(indices_rom[_T_1342], 1, 0)
    node _T_1357 = mux(_T_1301, _T_1339, twiddle_rom[_T_1350]) @[FFT.scala 49:49]
    node _T_1359 = add(start, UInt<1>("h01")) @[FFT.scala 49:67]
    node _T_1360 = tail(_T_1359, 1) @[FFT.scala 49:67]
    node _T_1362 = bits(indices_rom[_T_1360], 2, 2) @[FFT.scala 49:76]
    node _T_1364 = add(start, UInt<1>("h01")) @[FFT.scala 49:150]
    node _T_1365 = tail(_T_1364, 1) @[FFT.scala 49:150]
    node _T_1367 = bits(indices_rom[_T_1365], 1, 0) @[FFT.scala 49:159]
    wire _T_1377 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1377 is invalid @[DspReal.scala 165:19]
    _T_1377.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_1_1 of BBFSubtract_1 @[DspReal.scala 102:36]
    BBFSubtract_1_1.out is invalid
    BBFSubtract_1_1.in2 is invalid
    BBFSubtract_1_1.in1 is invalid
    BBFSubtract_1_1.in1 <= _T_1377.node @[DspReal.scala 81:21]
    BBFSubtract_1_1.in2 <= twiddle_rom[_T_1367].real.node @[DspReal.scala 82:21]
    wire _T_1384 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_1384 is invalid @[DspReal.scala 83:19]
    _T_1384.node <= BBFSubtract_1_1.out @[DspReal.scala 84:14]
    wire _T_1400 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_1400 is invalid @[DspComplex.scala 14:22]
    _T_1400.real.node <= twiddle_rom[_T_1367].imaginary.node @[DspComplex.scala 15:17]
    _T_1400.imaginary.node <= _T_1384.node @[DspComplex.scala 16:22]
    node _T_1402 = add(start, UInt<1>("h01")) @[FFT.scala 49:219]
    node _T_1403 = tail(_T_1402, 1) @[FFT.scala 49:219]
    node _T_1411 = bits(indices_rom[_T_1403], 1, 0)
    node _T_1418 = mux(_T_1362, _T_1400, twiddle_rom[_T_1411]) @[FFT.scala 49:49]
    node _T_1420 = add(start, UInt<2>("h02")) @[FFT.scala 49:67]
    node _T_1421 = tail(_T_1420, 1) @[FFT.scala 49:67]
    node _T_1423 = bits(indices_rom[_T_1421], 2, 2) @[FFT.scala 49:76]
    node _T_1425 = add(start, UInt<2>("h02")) @[FFT.scala 49:150]
    node _T_1426 = tail(_T_1425, 1) @[FFT.scala 49:150]
    node _T_1428 = bits(indices_rom[_T_1426], 1, 0) @[FFT.scala 49:159]
    wire _T_1438 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1438 is invalid @[DspReal.scala 165:19]
    _T_1438.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_2_1 of BBFSubtract_2 @[DspReal.scala 102:36]
    BBFSubtract_2_1.out is invalid
    BBFSubtract_2_1.in2 is invalid
    BBFSubtract_2_1.in1 is invalid
    BBFSubtract_2_1.in1 <= _T_1438.node @[DspReal.scala 81:21]
    BBFSubtract_2_1.in2 <= twiddle_rom[_T_1428].real.node @[DspReal.scala 82:21]
    wire _T_1445 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_1445 is invalid @[DspReal.scala 83:19]
    _T_1445.node <= BBFSubtract_2_1.out @[DspReal.scala 84:14]
    wire _T_1461 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_1461 is invalid @[DspComplex.scala 14:22]
    _T_1461.real.node <= twiddle_rom[_T_1428].imaginary.node @[DspComplex.scala 15:17]
    _T_1461.imaginary.node <= _T_1445.node @[DspComplex.scala 16:22]
    node _T_1463 = add(start, UInt<2>("h02")) @[FFT.scala 49:219]
    node _T_1464 = tail(_T_1463, 1) @[FFT.scala 49:219]
    node _T_1472 = bits(indices_rom[_T_1464], 1, 0)
    node _T_1479 = mux(_T_1423, _T_1461, twiddle_rom[_T_1472]) @[FFT.scala 49:49]
    node _T_1481 = add(start, UInt<2>("h03")) @[FFT.scala 49:67]
    node _T_1482 = tail(_T_1481, 1) @[FFT.scala 49:67]
    node _T_1484 = bits(indices_rom[_T_1482], 2, 2) @[FFT.scala 49:76]
    node _T_1486 = add(start, UInt<2>("h03")) @[FFT.scala 49:150]
    node _T_1487 = tail(_T_1486, 1) @[FFT.scala 49:150]
    node _T_1489 = bits(indices_rom[_T_1487], 1, 0) @[FFT.scala 49:159]
    wire _T_1499 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1499 is invalid @[DspReal.scala 165:19]
    _T_1499.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_3_1 of BBFSubtract_3 @[DspReal.scala 102:36]
    BBFSubtract_3_1.out is invalid
    BBFSubtract_3_1.in2 is invalid
    BBFSubtract_3_1.in1 is invalid
    BBFSubtract_3_1.in1 <= _T_1499.node @[DspReal.scala 81:21]
    BBFSubtract_3_1.in2 <= twiddle_rom[_T_1489].real.node @[DspReal.scala 82:21]
    wire _T_1506 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_1506 is invalid @[DspReal.scala 83:19]
    _T_1506.node <= BBFSubtract_3_1.out @[DspReal.scala 84:14]
    wire _T_1522 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_1522 is invalid @[DspComplex.scala 14:22]
    _T_1522.real.node <= twiddle_rom[_T_1489].imaginary.node @[DspComplex.scala 15:17]
    _T_1522.imaginary.node <= _T_1506.node @[DspComplex.scala 16:22]
    node _T_1524 = add(start, UInt<2>("h03")) @[FFT.scala 49:219]
    node _T_1525 = tail(_T_1524, 1) @[FFT.scala 49:219]
    node _T_1533 = bits(indices_rom[_T_1525], 1, 0)
    node _T_1540 = mux(_T_1484, _T_1522, twiddle_rom[_T_1533]) @[FFT.scala 49:49]
    node _T_1542 = add(start, UInt<3>("h04")) @[FFT.scala 49:67]
    node _T_1543 = tail(_T_1542, 1) @[FFT.scala 49:67]
    node _T_1545 = bits(indices_rom[_T_1543], 2, 2) @[FFT.scala 49:76]
    node _T_1547 = add(start, UInt<3>("h04")) @[FFT.scala 49:150]
    node _T_1548 = tail(_T_1547, 1) @[FFT.scala 49:150]
    node _T_1550 = bits(indices_rom[_T_1548], 1, 0) @[FFT.scala 49:159]
    wire _T_1560 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1560 is invalid @[DspReal.scala 165:19]
    _T_1560.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_4_1 of BBFSubtract_4 @[DspReal.scala 102:36]
    BBFSubtract_4_1.out is invalid
    BBFSubtract_4_1.in2 is invalid
    BBFSubtract_4_1.in1 is invalid
    BBFSubtract_4_1.in1 <= _T_1560.node @[DspReal.scala 81:21]
    BBFSubtract_4_1.in2 <= twiddle_rom[_T_1550].real.node @[DspReal.scala 82:21]
    wire _T_1567 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_1567 is invalid @[DspReal.scala 83:19]
    _T_1567.node <= BBFSubtract_4_1.out @[DspReal.scala 84:14]
    wire _T_1583 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_1583 is invalid @[DspComplex.scala 14:22]
    _T_1583.real.node <= twiddle_rom[_T_1550].imaginary.node @[DspComplex.scala 15:17]
    _T_1583.imaginary.node <= _T_1567.node @[DspComplex.scala 16:22]
    node _T_1585 = add(start, UInt<3>("h04")) @[FFT.scala 49:219]
    node _T_1586 = tail(_T_1585, 1) @[FFT.scala 49:219]
    node _T_1594 = bits(indices_rom[_T_1586], 1, 0)
    node _T_1601 = mux(_T_1545, _T_1583, twiddle_rom[_T_1594]) @[FFT.scala 49:49]
    node _T_1603 = add(start, UInt<3>("h05")) @[FFT.scala 49:67]
    node _T_1604 = tail(_T_1603, 1) @[FFT.scala 49:67]
    node _T_1606 = bits(indices_rom[_T_1604], 2, 2) @[FFT.scala 49:76]
    node _T_1608 = add(start, UInt<3>("h05")) @[FFT.scala 49:150]
    node _T_1609 = tail(_T_1608, 1) @[FFT.scala 49:150]
    node _T_1611 = bits(indices_rom[_T_1609], 1, 0) @[FFT.scala 49:159]
    wire _T_1621 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1621 is invalid @[DspReal.scala 165:19]
    _T_1621.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_5_1 of BBFSubtract_5 @[DspReal.scala 102:36]
    BBFSubtract_5_1.out is invalid
    BBFSubtract_5_1.in2 is invalid
    BBFSubtract_5_1.in1 is invalid
    BBFSubtract_5_1.in1 <= _T_1621.node @[DspReal.scala 81:21]
    BBFSubtract_5_1.in2 <= twiddle_rom[_T_1611].real.node @[DspReal.scala 82:21]
    wire _T_1628 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_1628 is invalid @[DspReal.scala 83:19]
    _T_1628.node <= BBFSubtract_5_1.out @[DspReal.scala 84:14]
    wire _T_1644 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_1644 is invalid @[DspComplex.scala 14:22]
    _T_1644.real.node <= twiddle_rom[_T_1611].imaginary.node @[DspComplex.scala 15:17]
    _T_1644.imaginary.node <= _T_1628.node @[DspComplex.scala 16:22]
    node _T_1646 = add(start, UInt<3>("h05")) @[FFT.scala 49:219]
    node _T_1647 = tail(_T_1646, 1) @[FFT.scala 49:219]
    node _T_1655 = bits(indices_rom[_T_1647], 1, 0)
    node _T_1662 = mux(_T_1606, _T_1644, twiddle_rom[_T_1655]) @[FFT.scala 49:49]
    node _T_1664 = add(start, UInt<3>("h06")) @[FFT.scala 49:67]
    node _T_1665 = tail(_T_1664, 1) @[FFT.scala 49:67]
    node _T_1667 = bits(indices_rom[_T_1665], 2, 2) @[FFT.scala 49:76]
    node _T_1669 = add(start, UInt<3>("h06")) @[FFT.scala 49:150]
    node _T_1670 = tail(_T_1669, 1) @[FFT.scala 49:150]
    node _T_1672 = bits(indices_rom[_T_1670], 1, 0) @[FFT.scala 49:159]
    wire _T_1682 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1682 is invalid @[DspReal.scala 165:19]
    _T_1682.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_6_1 of BBFSubtract_6 @[DspReal.scala 102:36]
    BBFSubtract_6_1.out is invalid
    BBFSubtract_6_1.in2 is invalid
    BBFSubtract_6_1.in1 is invalid
    BBFSubtract_6_1.in1 <= _T_1682.node @[DspReal.scala 81:21]
    BBFSubtract_6_1.in2 <= twiddle_rom[_T_1672].real.node @[DspReal.scala 82:21]
    wire _T_1689 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_1689 is invalid @[DspReal.scala 83:19]
    _T_1689.node <= BBFSubtract_6_1.out @[DspReal.scala 84:14]
    wire _T_1705 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_1705 is invalid @[DspComplex.scala 14:22]
    _T_1705.real.node <= twiddle_rom[_T_1672].imaginary.node @[DspComplex.scala 15:17]
    _T_1705.imaginary.node <= _T_1689.node @[DspComplex.scala 16:22]
    node _T_1707 = add(start, UInt<3>("h06")) @[FFT.scala 49:219]
    node _T_1708 = tail(_T_1707, 1) @[FFT.scala 49:219]
    node _T_1716 = bits(indices_rom[_T_1708], 1, 0)
    node _T_1723 = mux(_T_1667, _T_1705, twiddle_rom[_T_1716]) @[FFT.scala 49:49]
    twiddle[0].imaginary.node <= _T_1357.imaginary.node @[FFT.scala 49:13]
    twiddle[0].real.node <= _T_1357.real.node @[FFT.scala 49:13]
    twiddle[1].imaginary.node <= _T_1418.imaginary.node @[FFT.scala 49:13]
    twiddle[1].real.node <= _T_1418.real.node @[FFT.scala 49:13]
    twiddle[2].imaginary.node <= _T_1479.imaginary.node @[FFT.scala 49:13]
    twiddle[2].real.node <= _T_1479.real.node @[FFT.scala 49:13]
    twiddle[3].imaginary.node <= _T_1540.imaginary.node @[FFT.scala 49:13]
    twiddle[3].real.node <= _T_1540.real.node @[FFT.scala 49:13]
    twiddle[4].imaginary.node <= _T_1601.imaginary.node @[FFT.scala 49:13]
    twiddle[4].real.node <= _T_1601.real.node @[FFT.scala 49:13]
    twiddle[5].imaginary.node <= _T_1662.imaginary.node @[FFT.scala 49:13]
    twiddle[5].real.node <= _T_1662.real.node @[FFT.scala 49:13]
    twiddle[6].imaginary.node <= _T_1723.imaginary.node @[FFT.scala 49:13]
    twiddle[6].real.node <= _T_1723.real.node @[FFT.scala 49:13]
    wire _T_1727 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1727 is invalid @[DspReal.scala 165:19]
    _T_1727.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1734 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1734 is invalid @[DspReal.scala 165:19]
    _T_1734.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_0_0 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 54:77]
    stage_outputs_0_0 is invalid @[FFT.scala 54:77]
    wire _T_1754 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1754 is invalid @[DspReal.scala 165:19]
    _T_1754.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1761 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1761 is invalid @[DspReal.scala 165:19]
    _T_1761.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_0_1 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 54:77]
    stage_outputs_0_1 is invalid @[FFT.scala 54:77]
    wire _T_1781 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1781 is invalid @[DspReal.scala 165:19]
    _T_1781.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1788 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1788 is invalid @[DspReal.scala 165:19]
    _T_1788.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_0_2 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 54:77]
    stage_outputs_0_2 is invalid @[FFT.scala 54:77]
    wire _T_1808 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1808 is invalid @[DspReal.scala 165:19]
    _T_1808.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1815 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1815 is invalid @[DspReal.scala 165:19]
    _T_1815.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_0_3 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 54:77]
    stage_outputs_0_3 is invalid @[FFT.scala 54:77]
    wire _T_1835 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1835 is invalid @[DspReal.scala 165:19]
    _T_1835.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1842 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1842 is invalid @[DspReal.scala 165:19]
    _T_1842.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_0_4 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 54:77]
    stage_outputs_0_4 is invalid @[FFT.scala 54:77]
    wire _T_1862 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1862 is invalid @[DspReal.scala 165:19]
    _T_1862.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1869 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1869 is invalid @[DspReal.scala 165:19]
    _T_1869.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_0_5 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 54:77]
    stage_outputs_0_5 is invalid @[FFT.scala 54:77]
    wire _T_1889 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1889 is invalid @[DspReal.scala 165:19]
    _T_1889.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1896 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1896 is invalid @[DspReal.scala 165:19]
    _T_1896.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_0_6 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 54:77]
    stage_outputs_0_6 is invalid @[FFT.scala 54:77]
    wire _T_1916 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1916 is invalid @[DspReal.scala 165:19]
    _T_1916.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1923 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1923 is invalid @[DspReal.scala 165:19]
    _T_1923.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_0_7 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 54:77]
    stage_outputs_0_7 is invalid @[FFT.scala 54:77]
    wire _T_1943 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1943 is invalid @[DspReal.scala 165:19]
    _T_1943.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1950 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1950 is invalid @[DspReal.scala 165:19]
    _T_1950.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_1_0 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 54:77]
    stage_outputs_1_0 is invalid @[FFT.scala 54:77]
    wire _T_1970 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1970 is invalid @[DspReal.scala 165:19]
    _T_1970.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1977 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1977 is invalid @[DspReal.scala 165:19]
    _T_1977.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_1_1 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 54:77]
    stage_outputs_1_1 is invalid @[FFT.scala 54:77]
    wire _T_1997 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1997 is invalid @[DspReal.scala 165:19]
    _T_1997.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_2004 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2004 is invalid @[DspReal.scala 165:19]
    _T_2004.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_1_2 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 54:77]
    stage_outputs_1_2 is invalid @[FFT.scala 54:77]
    wire _T_2024 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2024 is invalid @[DspReal.scala 165:19]
    _T_2024.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_2031 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2031 is invalid @[DspReal.scala 165:19]
    _T_2031.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_1_3 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 54:77]
    stage_outputs_1_3 is invalid @[FFT.scala 54:77]
    wire _T_2051 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2051 is invalid @[DspReal.scala 165:19]
    _T_2051.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_2058 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2058 is invalid @[DspReal.scala 165:19]
    _T_2058.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_1_4 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 54:77]
    stage_outputs_1_4 is invalid @[FFT.scala 54:77]
    wire _T_2078 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2078 is invalid @[DspReal.scala 165:19]
    _T_2078.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_2085 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2085 is invalid @[DspReal.scala 165:19]
    _T_2085.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_1_5 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 54:77]
    stage_outputs_1_5 is invalid @[FFT.scala 54:77]
    wire _T_2105 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2105 is invalid @[DspReal.scala 165:19]
    _T_2105.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_2112 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2112 is invalid @[DspReal.scala 165:19]
    _T_2112.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_1_6 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 54:77]
    stage_outputs_1_6 is invalid @[FFT.scala 54:77]
    wire _T_2132 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2132 is invalid @[DspReal.scala 165:19]
    _T_2132.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_2139 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2139 is invalid @[DspReal.scala 165:19]
    _T_2139.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_1_7 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 54:77]
    stage_outputs_1_7 is invalid @[FFT.scala 54:77]
    wire _T_2159 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2159 is invalid @[DspReal.scala 165:19]
    _T_2159.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_2166 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2166 is invalid @[DspReal.scala 165:19]
    _T_2166.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_2_0 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 54:77]
    stage_outputs_2_0 is invalid @[FFT.scala 54:77]
    wire _T_2186 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2186 is invalid @[DspReal.scala 165:19]
    _T_2186.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_2193 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2193 is invalid @[DspReal.scala 165:19]
    _T_2193.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_2_1 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 54:77]
    stage_outputs_2_1 is invalid @[FFT.scala 54:77]
    wire _T_2213 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2213 is invalid @[DspReal.scala 165:19]
    _T_2213.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_2220 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2220 is invalid @[DspReal.scala 165:19]
    _T_2220.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_2_2 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 54:77]
    stage_outputs_2_2 is invalid @[FFT.scala 54:77]
    wire _T_2240 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2240 is invalid @[DspReal.scala 165:19]
    _T_2240.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_2247 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2247 is invalid @[DspReal.scala 165:19]
    _T_2247.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_2_3 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 54:77]
    stage_outputs_2_3 is invalid @[FFT.scala 54:77]
    wire _T_2267 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2267 is invalid @[DspReal.scala 165:19]
    _T_2267.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_2274 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2274 is invalid @[DspReal.scala 165:19]
    _T_2274.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_2_4 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 54:77]
    stage_outputs_2_4 is invalid @[FFT.scala 54:77]
    wire _T_2294 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2294 is invalid @[DspReal.scala 165:19]
    _T_2294.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_2301 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2301 is invalid @[DspReal.scala 165:19]
    _T_2301.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_2_5 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 54:77]
    stage_outputs_2_5 is invalid @[FFT.scala 54:77]
    wire _T_2321 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2321 is invalid @[DspReal.scala 165:19]
    _T_2321.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_2328 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2328 is invalid @[DspReal.scala 165:19]
    _T_2328.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_2_6 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 54:77]
    stage_outputs_2_6 is invalid @[FFT.scala 54:77]
    wire _T_2348 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2348 is invalid @[DspReal.scala 165:19]
    _T_2348.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_2355 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2355 is invalid @[DspReal.scala 165:19]
    _T_2355.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_2_7 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 54:77]
    stage_outputs_2_7 is invalid @[FFT.scala 54:77]
    wire _T_2375 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2375 is invalid @[DspReal.scala 165:19]
    _T_2375.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_2382 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2382 is invalid @[DspReal.scala 165:19]
    _T_2382.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_3_0 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 54:77]
    stage_outputs_3_0 is invalid @[FFT.scala 54:77]
    wire _T_2402 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2402 is invalid @[DspReal.scala 165:19]
    _T_2402.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_2409 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2409 is invalid @[DspReal.scala 165:19]
    _T_2409.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_3_1 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 54:77]
    stage_outputs_3_1 is invalid @[FFT.scala 54:77]
    wire _T_2429 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2429 is invalid @[DspReal.scala 165:19]
    _T_2429.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_2436 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2436 is invalid @[DspReal.scala 165:19]
    _T_2436.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_3_2 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 54:77]
    stage_outputs_3_2 is invalid @[FFT.scala 54:77]
    wire _T_2456 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2456 is invalid @[DspReal.scala 165:19]
    _T_2456.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_2463 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2463 is invalid @[DspReal.scala 165:19]
    _T_2463.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_3_3 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 54:77]
    stage_outputs_3_3 is invalid @[FFT.scala 54:77]
    wire _T_2483 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2483 is invalid @[DspReal.scala 165:19]
    _T_2483.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_2490 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2490 is invalid @[DspReal.scala 165:19]
    _T_2490.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_3_4 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 54:77]
    stage_outputs_3_4 is invalid @[FFT.scala 54:77]
    wire _T_2510 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2510 is invalid @[DspReal.scala 165:19]
    _T_2510.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_2517 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2517 is invalid @[DspReal.scala 165:19]
    _T_2517.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_3_5 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 54:77]
    stage_outputs_3_5 is invalid @[FFT.scala 54:77]
    wire _T_2537 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2537 is invalid @[DspReal.scala 165:19]
    _T_2537.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_2544 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2544 is invalid @[DspReal.scala 165:19]
    _T_2544.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_3_6 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 54:77]
    stage_outputs_3_6 is invalid @[FFT.scala 54:77]
    wire _T_2564 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2564 is invalid @[DspReal.scala 165:19]
    _T_2564.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_2571 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2571 is invalid @[DspReal.scala 165:19]
    _T_2571.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_3_7 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 54:77]
    stage_outputs_3_7 is invalid @[FFT.scala 54:77]
    stage_outputs_0_0.imaginary.node <= io.in.bits[0].imaginary.node @[FFT.scala 55:67]
    stage_outputs_0_0.real.node <= io.in.bits[0].real.node @[FFT.scala 55:67]
    stage_outputs_0_1.imaginary.node <= io.in.bits[1].imaginary.node @[FFT.scala 55:67]
    stage_outputs_0_1.real.node <= io.in.bits[1].real.node @[FFT.scala 55:67]
    stage_outputs_0_2.imaginary.node <= io.in.bits[2].imaginary.node @[FFT.scala 55:67]
    stage_outputs_0_2.real.node <= io.in.bits[2].real.node @[FFT.scala 55:67]
    stage_outputs_0_3.imaginary.node <= io.in.bits[3].imaginary.node @[FFT.scala 55:67]
    stage_outputs_0_3.real.node <= io.in.bits[3].real.node @[FFT.scala 55:67]
    stage_outputs_0_4.imaginary.node <= io.in.bits[4].imaginary.node @[FFT.scala 55:67]
    stage_outputs_0_4.real.node <= io.in.bits[4].real.node @[FFT.scala 55:67]
    stage_outputs_0_5.imaginary.node <= io.in.bits[5].imaginary.node @[FFT.scala 55:67]
    stage_outputs_0_5.real.node <= io.in.bits[5].real.node @[FFT.scala 55:67]
    stage_outputs_0_6.imaginary.node <= io.in.bits[6].imaginary.node @[FFT.scala 55:67]
    stage_outputs_0_6.real.node <= io.in.bits[6].real.node @[FFT.scala 55:67]
    stage_outputs_0_7.imaginary.node <= io.in.bits[7].imaginary.node @[FFT.scala 55:67]
    stage_outputs_0_7.real.node <= io.in.bits[7].real.node @[FFT.scala 55:67]
    inst BBFMultiply_48 of BBFMultiply @[DspReal.scala 106:36]
    BBFMultiply_48.out is invalid
    BBFMultiply_48.in2 is invalid
    BBFMultiply_48.in1 is invalid
    BBFMultiply_48.in1 <= stage_outputs_0_4.real.node @[DspReal.scala 81:21]
    BBFMultiply_48.in2 <= twiddle[0].real.node @[DspReal.scala 82:21]
    wire _T_2591 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2591 is invalid @[DspReal.scala 83:19]
    _T_2591.node <= BBFMultiply_48.out @[DspReal.scala 84:14]
    inst BBFMultiply_1_1 of BBFMultiply_1 @[DspReal.scala 106:36]
    BBFMultiply_1_1.out is invalid
    BBFMultiply_1_1.in2 is invalid
    BBFMultiply_1_1.in1 is invalid
    BBFMultiply_1_1.in1 <= stage_outputs_0_4.imaginary.node @[DspReal.scala 81:21]
    BBFMultiply_1_1.in2 <= twiddle[0].imaginary.node @[DspReal.scala 82:21]
    wire _T_2597 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2597 is invalid @[DspReal.scala 83:19]
    _T_2597.node <= BBFMultiply_1_1.out @[DspReal.scala 84:14]
    wire _T_2603 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2603 is invalid @[DspReal.scala 165:19]
    _T_2603.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_7_1 of BBFSubtract_7 @[DspReal.scala 102:36]
    BBFSubtract_7_1.out is invalid
    BBFSubtract_7_1.in2 is invalid
    BBFSubtract_7_1.in1 is invalid
    BBFSubtract_7_1.in1 <= _T_2603.node @[DspReal.scala 81:21]
    BBFSubtract_7_1.in2 <= _T_2597.node @[DspReal.scala 82:21]
    wire _T_2610 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2610 is invalid @[DspReal.scala 83:19]
    _T_2610.node <= BBFSubtract_7_1.out @[DspReal.scala 84:14]
    inst BBFAdd_72 of BBFAdd @[DspReal.scala 98:36]
    BBFAdd_72.out is invalid
    BBFAdd_72.in2 is invalid
    BBFAdd_72.in1 is invalid
    BBFAdd_72.in1 <= _T_2591.node @[DspReal.scala 81:21]
    BBFAdd_72.in2 <= _T_2610.node @[DspReal.scala 82:21]
    wire _T_2616 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2616 is invalid @[DspReal.scala 83:19]
    _T_2616.node <= BBFAdd_72.out @[DspReal.scala 84:14]
    inst BBFMultiply_2_1 of BBFMultiply_2 @[DspReal.scala 106:36]
    BBFMultiply_2_1.out is invalid
    BBFMultiply_2_1.in2 is invalid
    BBFMultiply_2_1.in1 is invalid
    BBFMultiply_2_1.in1 <= stage_outputs_0_4.real.node @[DspReal.scala 81:21]
    BBFMultiply_2_1.in2 <= twiddle[0].imaginary.node @[DspReal.scala 82:21]
    wire _T_2622 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2622 is invalid @[DspReal.scala 83:19]
    _T_2622.node <= BBFMultiply_2_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_3_1 of BBFMultiply_3 @[DspReal.scala 106:36]
    BBFMultiply_3_1.out is invalid
    BBFMultiply_3_1.in2 is invalid
    BBFMultiply_3_1.in1 is invalid
    BBFMultiply_3_1.in1 <= stage_outputs_0_4.imaginary.node @[DspReal.scala 81:21]
    BBFMultiply_3_1.in2 <= twiddle[0].real.node @[DspReal.scala 82:21]
    wire _T_2628 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2628 is invalid @[DspReal.scala 83:19]
    _T_2628.node <= BBFMultiply_3_1.out @[DspReal.scala 84:14]
    inst BBFAdd_1_1 of BBFAdd_1 @[DspReal.scala 98:36]
    BBFAdd_1_1.out is invalid
    BBFAdd_1_1.in2 is invalid
    BBFAdd_1_1.in1 is invalid
    BBFAdd_1_1.in1 <= _T_2622.node @[DspReal.scala 81:21]
    BBFAdd_1_1.in2 <= _T_2628.node @[DspReal.scala 82:21]
    wire _T_2634 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2634 is invalid @[DspReal.scala 83:19]
    _T_2634.node <= BBFAdd_1_1.out @[DspReal.scala 84:14]
    wire _T_2650 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_2650 is invalid @[DspComplex.scala 14:22]
    _T_2650.real.node <= _T_2616.node @[DspComplex.scala 15:17]
    _T_2650.imaginary.node <= _T_2634.node @[DspComplex.scala 16:22]
    inst BBFAdd_2_1 of BBFAdd_2 @[DspReal.scala 98:36]
    BBFAdd_2_1.out is invalid
    BBFAdd_2_1.in2 is invalid
    BBFAdd_2_1.in1 is invalid
    BBFAdd_2_1.in1 <= stage_outputs_0_0.real.node @[DspReal.scala 81:21]
    BBFAdd_2_1.in2 <= _T_2650.real.node @[DspReal.scala 82:21]
    wire _T_2654 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2654 is invalid @[DspReal.scala 83:19]
    _T_2654.node <= BBFAdd_2_1.out @[DspReal.scala 84:14]
    inst BBFAdd_3_1 of BBFAdd_3 @[DspReal.scala 98:36]
    BBFAdd_3_1.out is invalid
    BBFAdd_3_1.in2 is invalid
    BBFAdd_3_1.in1 is invalid
    BBFAdd_3_1.in1 <= stage_outputs_0_0.imaginary.node @[DspReal.scala 81:21]
    BBFAdd_3_1.in2 <= _T_2650.imaginary.node @[DspReal.scala 82:21]
    wire _T_2660 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2660 is invalid @[DspReal.scala 83:19]
    _T_2660.node <= BBFAdd_3_1.out @[DspReal.scala 84:14]
    wire _T_2676 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_2676 is invalid @[DspComplex.scala 14:22]
    _T_2676.real.node <= _T_2654.node @[DspComplex.scala 15:17]
    _T_2676.imaginary.node <= _T_2660.node @[DspComplex.scala 16:22]
    wire _T_2680 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2680 is invalid @[DspReal.scala 165:19]
    _T_2680.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_8_1 of BBFSubtract_8 @[DspReal.scala 102:36]
    BBFSubtract_8_1.out is invalid
    BBFSubtract_8_1.in2 is invalid
    BBFSubtract_8_1.in1 is invalid
    BBFSubtract_8_1.in1 <= _T_2680.node @[DspReal.scala 81:21]
    BBFSubtract_8_1.in2 <= _T_2650.real.node @[DspReal.scala 82:21]
    wire _T_2687 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2687 is invalid @[DspReal.scala 83:19]
    _T_2687.node <= BBFSubtract_8_1.out @[DspReal.scala 84:14]
    wire _T_2693 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2693 is invalid @[DspReal.scala 165:19]
    _T_2693.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_9_1 of BBFSubtract_9 @[DspReal.scala 102:36]
    BBFSubtract_9_1.out is invalid
    BBFSubtract_9_1.in2 is invalid
    BBFSubtract_9_1.in1 is invalid
    BBFSubtract_9_1.in1 <= _T_2693.node @[DspReal.scala 81:21]
    BBFSubtract_9_1.in2 <= _T_2650.imaginary.node @[DspReal.scala 82:21]
    wire _T_2700 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2700 is invalid @[DspReal.scala 83:19]
    _T_2700.node <= BBFSubtract_9_1.out @[DspReal.scala 84:14]
    wire _T_2716 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_2716 is invalid @[DspComplex.scala 14:22]
    _T_2716.real.node <= _T_2687.node @[DspComplex.scala 15:17]
    _T_2716.imaginary.node <= _T_2700.node @[DspComplex.scala 16:22]
    inst BBFAdd_4_1 of BBFAdd_4 @[DspReal.scala 98:36]
    BBFAdd_4_1.out is invalid
    BBFAdd_4_1.in2 is invalid
    BBFAdd_4_1.in1 is invalid
    BBFAdd_4_1.in1 <= stage_outputs_0_0.real.node @[DspReal.scala 81:21]
    BBFAdd_4_1.in2 <= _T_2716.real.node @[DspReal.scala 82:21]
    wire _T_2720 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2720 is invalid @[DspReal.scala 83:19]
    _T_2720.node <= BBFAdd_4_1.out @[DspReal.scala 84:14]
    inst BBFAdd_5_1 of BBFAdd_5 @[DspReal.scala 98:36]
    BBFAdd_5_1.out is invalid
    BBFAdd_5_1.in2 is invalid
    BBFAdd_5_1.in1 is invalid
    BBFAdd_5_1.in1 <= stage_outputs_0_0.imaginary.node @[DspReal.scala 81:21]
    BBFAdd_5_1.in2 <= _T_2716.imaginary.node @[DspReal.scala 82:21]
    wire _T_2726 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2726 is invalid @[DspReal.scala 83:19]
    _T_2726.node <= BBFAdd_5_1.out @[DspReal.scala 84:14]
    wire _T_2742 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_2742 is invalid @[DspComplex.scala 14:22]
    _T_2742.real.node <= _T_2720.node @[DspComplex.scala 15:17]
    _T_2742.imaginary.node <= _T_2726.node @[DspComplex.scala 16:22]
    cmem _T_2757 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_2760 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_2768 = _T_2757[UInt<1>("h00")], clock
      _T_2768.imaginary.node <= _T_2676.imaginary.node @[FFTUtilities.scala 172:29]
      _T_2768.real.node <= _T_2676.real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_2776 = _T_2757[UInt<1>("h00")], clock
    stage_outputs_1_0.imaginary.node <= _T_2776.imaginary.node @[FFT.scala 75:14]
    stage_outputs_1_0.real.node <= _T_2776.real.node @[FFT.scala 75:14]
    cmem _T_2791 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_2794 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_2802 = _T_2791[UInt<1>("h00")], clock
      _T_2802.imaginary.node <= _T_2742.imaginary.node @[FFTUtilities.scala 172:29]
      _T_2802.real.node <= _T_2742.real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_2810 = _T_2791[UInt<1>("h00")], clock
    stage_outputs_1_4.imaginary.node <= _T_2810.imaginary.node @[FFT.scala 75:14]
    stage_outputs_1_4.real.node <= _T_2810.real.node @[FFT.scala 75:14]
    inst BBFMultiply_4_1 of BBFMultiply_4 @[DspReal.scala 106:36]
    BBFMultiply_4_1.out is invalid
    BBFMultiply_4_1.in2 is invalid
    BBFMultiply_4_1.in1 is invalid
    BBFMultiply_4_1.in1 <= stage_outputs_0_5.real.node @[DspReal.scala 81:21]
    BBFMultiply_4_1.in2 <= twiddle[0].real.node @[DspReal.scala 82:21]
    wire _T_2814 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2814 is invalid @[DspReal.scala 83:19]
    _T_2814.node <= BBFMultiply_4_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_5_1 of BBFMultiply_5 @[DspReal.scala 106:36]
    BBFMultiply_5_1.out is invalid
    BBFMultiply_5_1.in2 is invalid
    BBFMultiply_5_1.in1 is invalid
    BBFMultiply_5_1.in1 <= stage_outputs_0_5.imaginary.node @[DspReal.scala 81:21]
    BBFMultiply_5_1.in2 <= twiddle[0].imaginary.node @[DspReal.scala 82:21]
    wire _T_2820 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2820 is invalid @[DspReal.scala 83:19]
    _T_2820.node <= BBFMultiply_5_1.out @[DspReal.scala 84:14]
    wire _T_2826 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2826 is invalid @[DspReal.scala 165:19]
    _T_2826.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_10_1 of BBFSubtract_10 @[DspReal.scala 102:36]
    BBFSubtract_10_1.out is invalid
    BBFSubtract_10_1.in2 is invalid
    BBFSubtract_10_1.in1 is invalid
    BBFSubtract_10_1.in1 <= _T_2826.node @[DspReal.scala 81:21]
    BBFSubtract_10_1.in2 <= _T_2820.node @[DspReal.scala 82:21]
    wire _T_2833 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2833 is invalid @[DspReal.scala 83:19]
    _T_2833.node <= BBFSubtract_10_1.out @[DspReal.scala 84:14]
    inst BBFAdd_6_1 of BBFAdd_6 @[DspReal.scala 98:36]
    BBFAdd_6_1.out is invalid
    BBFAdd_6_1.in2 is invalid
    BBFAdd_6_1.in1 is invalid
    BBFAdd_6_1.in1 <= _T_2814.node @[DspReal.scala 81:21]
    BBFAdd_6_1.in2 <= _T_2833.node @[DspReal.scala 82:21]
    wire _T_2839 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2839 is invalid @[DspReal.scala 83:19]
    _T_2839.node <= BBFAdd_6_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_6_1 of BBFMultiply_6 @[DspReal.scala 106:36]
    BBFMultiply_6_1.out is invalid
    BBFMultiply_6_1.in2 is invalid
    BBFMultiply_6_1.in1 is invalid
    BBFMultiply_6_1.in1 <= stage_outputs_0_5.real.node @[DspReal.scala 81:21]
    BBFMultiply_6_1.in2 <= twiddle[0].imaginary.node @[DspReal.scala 82:21]
    wire _T_2845 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2845 is invalid @[DspReal.scala 83:19]
    _T_2845.node <= BBFMultiply_6_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_7_1 of BBFMultiply_7 @[DspReal.scala 106:36]
    BBFMultiply_7_1.out is invalid
    BBFMultiply_7_1.in2 is invalid
    BBFMultiply_7_1.in1 is invalid
    BBFMultiply_7_1.in1 <= stage_outputs_0_5.imaginary.node @[DspReal.scala 81:21]
    BBFMultiply_7_1.in2 <= twiddle[0].real.node @[DspReal.scala 82:21]
    wire _T_2851 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2851 is invalid @[DspReal.scala 83:19]
    _T_2851.node <= BBFMultiply_7_1.out @[DspReal.scala 84:14]
    inst BBFAdd_7_1 of BBFAdd_7 @[DspReal.scala 98:36]
    BBFAdd_7_1.out is invalid
    BBFAdd_7_1.in2 is invalid
    BBFAdd_7_1.in1 is invalid
    BBFAdd_7_1.in1 <= _T_2845.node @[DspReal.scala 81:21]
    BBFAdd_7_1.in2 <= _T_2851.node @[DspReal.scala 82:21]
    wire _T_2857 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2857 is invalid @[DspReal.scala 83:19]
    _T_2857.node <= BBFAdd_7_1.out @[DspReal.scala 84:14]
    wire _T_2873 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_2873 is invalid @[DspComplex.scala 14:22]
    _T_2873.real.node <= _T_2839.node @[DspComplex.scala 15:17]
    _T_2873.imaginary.node <= _T_2857.node @[DspComplex.scala 16:22]
    inst BBFAdd_8_1 of BBFAdd_8 @[DspReal.scala 98:36]
    BBFAdd_8_1.out is invalid
    BBFAdd_8_1.in2 is invalid
    BBFAdd_8_1.in1 is invalid
    BBFAdd_8_1.in1 <= stage_outputs_0_1.real.node @[DspReal.scala 81:21]
    BBFAdd_8_1.in2 <= _T_2873.real.node @[DspReal.scala 82:21]
    wire _T_2877 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2877 is invalid @[DspReal.scala 83:19]
    _T_2877.node <= BBFAdd_8_1.out @[DspReal.scala 84:14]
    inst BBFAdd_9_1 of BBFAdd_9 @[DspReal.scala 98:36]
    BBFAdd_9_1.out is invalid
    BBFAdd_9_1.in2 is invalid
    BBFAdd_9_1.in1 is invalid
    BBFAdd_9_1.in1 <= stage_outputs_0_1.imaginary.node @[DspReal.scala 81:21]
    BBFAdd_9_1.in2 <= _T_2873.imaginary.node @[DspReal.scala 82:21]
    wire _T_2883 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2883 is invalid @[DspReal.scala 83:19]
    _T_2883.node <= BBFAdd_9_1.out @[DspReal.scala 84:14]
    wire _T_2899 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_2899 is invalid @[DspComplex.scala 14:22]
    _T_2899.real.node <= _T_2877.node @[DspComplex.scala 15:17]
    _T_2899.imaginary.node <= _T_2883.node @[DspComplex.scala 16:22]
    wire _T_2903 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2903 is invalid @[DspReal.scala 165:19]
    _T_2903.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_11_1 of BBFSubtract_11 @[DspReal.scala 102:36]
    BBFSubtract_11_1.out is invalid
    BBFSubtract_11_1.in2 is invalid
    BBFSubtract_11_1.in1 is invalid
    BBFSubtract_11_1.in1 <= _T_2903.node @[DspReal.scala 81:21]
    BBFSubtract_11_1.in2 <= _T_2873.real.node @[DspReal.scala 82:21]
    wire _T_2910 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2910 is invalid @[DspReal.scala 83:19]
    _T_2910.node <= BBFSubtract_11_1.out @[DspReal.scala 84:14]
    wire _T_2916 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2916 is invalid @[DspReal.scala 165:19]
    _T_2916.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_12_1 of BBFSubtract_12 @[DspReal.scala 102:36]
    BBFSubtract_12_1.out is invalid
    BBFSubtract_12_1.in2 is invalid
    BBFSubtract_12_1.in1 is invalid
    BBFSubtract_12_1.in1 <= _T_2916.node @[DspReal.scala 81:21]
    BBFSubtract_12_1.in2 <= _T_2873.imaginary.node @[DspReal.scala 82:21]
    wire _T_2923 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2923 is invalid @[DspReal.scala 83:19]
    _T_2923.node <= BBFSubtract_12_1.out @[DspReal.scala 84:14]
    wire _T_2939 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_2939 is invalid @[DspComplex.scala 14:22]
    _T_2939.real.node <= _T_2910.node @[DspComplex.scala 15:17]
    _T_2939.imaginary.node <= _T_2923.node @[DspComplex.scala 16:22]
    inst BBFAdd_10_1 of BBFAdd_10 @[DspReal.scala 98:36]
    BBFAdd_10_1.out is invalid
    BBFAdd_10_1.in2 is invalid
    BBFAdd_10_1.in1 is invalid
    BBFAdd_10_1.in1 <= stage_outputs_0_1.real.node @[DspReal.scala 81:21]
    BBFAdd_10_1.in2 <= _T_2939.real.node @[DspReal.scala 82:21]
    wire _T_2943 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2943 is invalid @[DspReal.scala 83:19]
    _T_2943.node <= BBFAdd_10_1.out @[DspReal.scala 84:14]
    inst BBFAdd_11_1 of BBFAdd_11 @[DspReal.scala 98:36]
    BBFAdd_11_1.out is invalid
    BBFAdd_11_1.in2 is invalid
    BBFAdd_11_1.in1 is invalid
    BBFAdd_11_1.in1 <= stage_outputs_0_1.imaginary.node @[DspReal.scala 81:21]
    BBFAdd_11_1.in2 <= _T_2939.imaginary.node @[DspReal.scala 82:21]
    wire _T_2949 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2949 is invalid @[DspReal.scala 83:19]
    _T_2949.node <= BBFAdd_11_1.out @[DspReal.scala 84:14]
    wire _T_2965 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_2965 is invalid @[DspComplex.scala 14:22]
    _T_2965.real.node <= _T_2943.node @[DspComplex.scala 15:17]
    _T_2965.imaginary.node <= _T_2949.node @[DspComplex.scala 16:22]
    cmem _T_2980 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_2983 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_2991 = _T_2980[UInt<1>("h00")], clock
      _T_2991.imaginary.node <= _T_2899.imaginary.node @[FFTUtilities.scala 172:29]
      _T_2991.real.node <= _T_2899.real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_2999 = _T_2980[UInt<1>("h00")], clock
    stage_outputs_1_1.imaginary.node <= _T_2999.imaginary.node @[FFT.scala 75:14]
    stage_outputs_1_1.real.node <= _T_2999.real.node @[FFT.scala 75:14]
    cmem _T_3014 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_3017 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_3025 = _T_3014[UInt<1>("h00")], clock
      _T_3025.imaginary.node <= _T_2965.imaginary.node @[FFTUtilities.scala 172:29]
      _T_3025.real.node <= _T_2965.real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_3033 = _T_3014[UInt<1>("h00")], clock
    stage_outputs_1_5.imaginary.node <= _T_3033.imaginary.node @[FFT.scala 75:14]
    stage_outputs_1_5.real.node <= _T_3033.real.node @[FFT.scala 75:14]
    inst BBFMultiply_8_1 of BBFMultiply_8 @[DspReal.scala 106:36]
    BBFMultiply_8_1.out is invalid
    BBFMultiply_8_1.in2 is invalid
    BBFMultiply_8_1.in1 is invalid
    BBFMultiply_8_1.in1 <= stage_outputs_0_6.real.node @[DspReal.scala 81:21]
    BBFMultiply_8_1.in2 <= twiddle[0].real.node @[DspReal.scala 82:21]
    wire _T_3037 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3037 is invalid @[DspReal.scala 83:19]
    _T_3037.node <= BBFMultiply_8_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_9_1 of BBFMultiply_9 @[DspReal.scala 106:36]
    BBFMultiply_9_1.out is invalid
    BBFMultiply_9_1.in2 is invalid
    BBFMultiply_9_1.in1 is invalid
    BBFMultiply_9_1.in1 <= stage_outputs_0_6.imaginary.node @[DspReal.scala 81:21]
    BBFMultiply_9_1.in2 <= twiddle[0].imaginary.node @[DspReal.scala 82:21]
    wire _T_3043 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3043 is invalid @[DspReal.scala 83:19]
    _T_3043.node <= BBFMultiply_9_1.out @[DspReal.scala 84:14]
    wire _T_3049 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_3049 is invalid @[DspReal.scala 165:19]
    _T_3049.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_13_1 of BBFSubtract_13 @[DspReal.scala 102:36]
    BBFSubtract_13_1.out is invalid
    BBFSubtract_13_1.in2 is invalid
    BBFSubtract_13_1.in1 is invalid
    BBFSubtract_13_1.in1 <= _T_3049.node @[DspReal.scala 81:21]
    BBFSubtract_13_1.in2 <= _T_3043.node @[DspReal.scala 82:21]
    wire _T_3056 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3056 is invalid @[DspReal.scala 83:19]
    _T_3056.node <= BBFSubtract_13_1.out @[DspReal.scala 84:14]
    inst BBFAdd_12_1 of BBFAdd_12 @[DspReal.scala 98:36]
    BBFAdd_12_1.out is invalid
    BBFAdd_12_1.in2 is invalid
    BBFAdd_12_1.in1 is invalid
    BBFAdd_12_1.in1 <= _T_3037.node @[DspReal.scala 81:21]
    BBFAdd_12_1.in2 <= _T_3056.node @[DspReal.scala 82:21]
    wire _T_3062 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3062 is invalid @[DspReal.scala 83:19]
    _T_3062.node <= BBFAdd_12_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_10_1 of BBFMultiply_10 @[DspReal.scala 106:36]
    BBFMultiply_10_1.out is invalid
    BBFMultiply_10_1.in2 is invalid
    BBFMultiply_10_1.in1 is invalid
    BBFMultiply_10_1.in1 <= stage_outputs_0_6.real.node @[DspReal.scala 81:21]
    BBFMultiply_10_1.in2 <= twiddle[0].imaginary.node @[DspReal.scala 82:21]
    wire _T_3068 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3068 is invalid @[DspReal.scala 83:19]
    _T_3068.node <= BBFMultiply_10_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_11_1 of BBFMultiply_11 @[DspReal.scala 106:36]
    BBFMultiply_11_1.out is invalid
    BBFMultiply_11_1.in2 is invalid
    BBFMultiply_11_1.in1 is invalid
    BBFMultiply_11_1.in1 <= stage_outputs_0_6.imaginary.node @[DspReal.scala 81:21]
    BBFMultiply_11_1.in2 <= twiddle[0].real.node @[DspReal.scala 82:21]
    wire _T_3074 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3074 is invalid @[DspReal.scala 83:19]
    _T_3074.node <= BBFMultiply_11_1.out @[DspReal.scala 84:14]
    inst BBFAdd_13_1 of BBFAdd_13 @[DspReal.scala 98:36]
    BBFAdd_13_1.out is invalid
    BBFAdd_13_1.in2 is invalid
    BBFAdd_13_1.in1 is invalid
    BBFAdd_13_1.in1 <= _T_3068.node @[DspReal.scala 81:21]
    BBFAdd_13_1.in2 <= _T_3074.node @[DspReal.scala 82:21]
    wire _T_3080 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3080 is invalid @[DspReal.scala 83:19]
    _T_3080.node <= BBFAdd_13_1.out @[DspReal.scala 84:14]
    wire _T_3096 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_3096 is invalid @[DspComplex.scala 14:22]
    _T_3096.real.node <= _T_3062.node @[DspComplex.scala 15:17]
    _T_3096.imaginary.node <= _T_3080.node @[DspComplex.scala 16:22]
    inst BBFAdd_14_1 of BBFAdd_14 @[DspReal.scala 98:36]
    BBFAdd_14_1.out is invalid
    BBFAdd_14_1.in2 is invalid
    BBFAdd_14_1.in1 is invalid
    BBFAdd_14_1.in1 <= stage_outputs_0_2.real.node @[DspReal.scala 81:21]
    BBFAdd_14_1.in2 <= _T_3096.real.node @[DspReal.scala 82:21]
    wire _T_3100 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3100 is invalid @[DspReal.scala 83:19]
    _T_3100.node <= BBFAdd_14_1.out @[DspReal.scala 84:14]
    inst BBFAdd_15_1 of BBFAdd_15 @[DspReal.scala 98:36]
    BBFAdd_15_1.out is invalid
    BBFAdd_15_1.in2 is invalid
    BBFAdd_15_1.in1 is invalid
    BBFAdd_15_1.in1 <= stage_outputs_0_2.imaginary.node @[DspReal.scala 81:21]
    BBFAdd_15_1.in2 <= _T_3096.imaginary.node @[DspReal.scala 82:21]
    wire _T_3106 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3106 is invalid @[DspReal.scala 83:19]
    _T_3106.node <= BBFAdd_15_1.out @[DspReal.scala 84:14]
    wire _T_3122 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_3122 is invalid @[DspComplex.scala 14:22]
    _T_3122.real.node <= _T_3100.node @[DspComplex.scala 15:17]
    _T_3122.imaginary.node <= _T_3106.node @[DspComplex.scala 16:22]
    wire _T_3126 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_3126 is invalid @[DspReal.scala 165:19]
    _T_3126.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_14_1 of BBFSubtract_14 @[DspReal.scala 102:36]
    BBFSubtract_14_1.out is invalid
    BBFSubtract_14_1.in2 is invalid
    BBFSubtract_14_1.in1 is invalid
    BBFSubtract_14_1.in1 <= _T_3126.node @[DspReal.scala 81:21]
    BBFSubtract_14_1.in2 <= _T_3096.real.node @[DspReal.scala 82:21]
    wire _T_3133 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3133 is invalid @[DspReal.scala 83:19]
    _T_3133.node <= BBFSubtract_14_1.out @[DspReal.scala 84:14]
    wire _T_3139 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_3139 is invalid @[DspReal.scala 165:19]
    _T_3139.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_15_1 of BBFSubtract_15 @[DspReal.scala 102:36]
    BBFSubtract_15_1.out is invalid
    BBFSubtract_15_1.in2 is invalid
    BBFSubtract_15_1.in1 is invalid
    BBFSubtract_15_1.in1 <= _T_3139.node @[DspReal.scala 81:21]
    BBFSubtract_15_1.in2 <= _T_3096.imaginary.node @[DspReal.scala 82:21]
    wire _T_3146 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3146 is invalid @[DspReal.scala 83:19]
    _T_3146.node <= BBFSubtract_15_1.out @[DspReal.scala 84:14]
    wire _T_3162 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_3162 is invalid @[DspComplex.scala 14:22]
    _T_3162.real.node <= _T_3133.node @[DspComplex.scala 15:17]
    _T_3162.imaginary.node <= _T_3146.node @[DspComplex.scala 16:22]
    inst BBFAdd_16_1 of BBFAdd_16 @[DspReal.scala 98:36]
    BBFAdd_16_1.out is invalid
    BBFAdd_16_1.in2 is invalid
    BBFAdd_16_1.in1 is invalid
    BBFAdd_16_1.in1 <= stage_outputs_0_2.real.node @[DspReal.scala 81:21]
    BBFAdd_16_1.in2 <= _T_3162.real.node @[DspReal.scala 82:21]
    wire _T_3166 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3166 is invalid @[DspReal.scala 83:19]
    _T_3166.node <= BBFAdd_16_1.out @[DspReal.scala 84:14]
    inst BBFAdd_17_1 of BBFAdd_17 @[DspReal.scala 98:36]
    BBFAdd_17_1.out is invalid
    BBFAdd_17_1.in2 is invalid
    BBFAdd_17_1.in1 is invalid
    BBFAdd_17_1.in1 <= stage_outputs_0_2.imaginary.node @[DspReal.scala 81:21]
    BBFAdd_17_1.in2 <= _T_3162.imaginary.node @[DspReal.scala 82:21]
    wire _T_3172 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3172 is invalid @[DspReal.scala 83:19]
    _T_3172.node <= BBFAdd_17_1.out @[DspReal.scala 84:14]
    wire _T_3188 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_3188 is invalid @[DspComplex.scala 14:22]
    _T_3188.real.node <= _T_3166.node @[DspComplex.scala 15:17]
    _T_3188.imaginary.node <= _T_3172.node @[DspComplex.scala 16:22]
    cmem _T_3203 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_3206 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_3214 = _T_3203[UInt<1>("h00")], clock
      _T_3214.imaginary.node <= _T_3122.imaginary.node @[FFTUtilities.scala 172:29]
      _T_3214.real.node <= _T_3122.real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_3222 = _T_3203[UInt<1>("h00")], clock
    stage_outputs_1_2.imaginary.node <= _T_3222.imaginary.node @[FFT.scala 75:14]
    stage_outputs_1_2.real.node <= _T_3222.real.node @[FFT.scala 75:14]
    cmem _T_3237 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_3240 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_3248 = _T_3237[UInt<1>("h00")], clock
      _T_3248.imaginary.node <= _T_3188.imaginary.node @[FFTUtilities.scala 172:29]
      _T_3248.real.node <= _T_3188.real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_3256 = _T_3237[UInt<1>("h00")], clock
    stage_outputs_1_6.imaginary.node <= _T_3256.imaginary.node @[FFT.scala 75:14]
    stage_outputs_1_6.real.node <= _T_3256.real.node @[FFT.scala 75:14]
    inst BBFMultiply_12_1 of BBFMultiply_12 @[DspReal.scala 106:36]
    BBFMultiply_12_1.out is invalid
    BBFMultiply_12_1.in2 is invalid
    BBFMultiply_12_1.in1 is invalid
    BBFMultiply_12_1.in1 <= stage_outputs_0_7.real.node @[DspReal.scala 81:21]
    BBFMultiply_12_1.in2 <= twiddle[0].real.node @[DspReal.scala 82:21]
    wire _T_3260 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3260 is invalid @[DspReal.scala 83:19]
    _T_3260.node <= BBFMultiply_12_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_13_1 of BBFMultiply_13 @[DspReal.scala 106:36]
    BBFMultiply_13_1.out is invalid
    BBFMultiply_13_1.in2 is invalid
    BBFMultiply_13_1.in1 is invalid
    BBFMultiply_13_1.in1 <= stage_outputs_0_7.imaginary.node @[DspReal.scala 81:21]
    BBFMultiply_13_1.in2 <= twiddle[0].imaginary.node @[DspReal.scala 82:21]
    wire _T_3266 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3266 is invalid @[DspReal.scala 83:19]
    _T_3266.node <= BBFMultiply_13_1.out @[DspReal.scala 84:14]
    wire _T_3272 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_3272 is invalid @[DspReal.scala 165:19]
    _T_3272.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_16_1 of BBFSubtract_16 @[DspReal.scala 102:36]
    BBFSubtract_16_1.out is invalid
    BBFSubtract_16_1.in2 is invalid
    BBFSubtract_16_1.in1 is invalid
    BBFSubtract_16_1.in1 <= _T_3272.node @[DspReal.scala 81:21]
    BBFSubtract_16_1.in2 <= _T_3266.node @[DspReal.scala 82:21]
    wire _T_3279 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3279 is invalid @[DspReal.scala 83:19]
    _T_3279.node <= BBFSubtract_16_1.out @[DspReal.scala 84:14]
    inst BBFAdd_18_1 of BBFAdd_18 @[DspReal.scala 98:36]
    BBFAdd_18_1.out is invalid
    BBFAdd_18_1.in2 is invalid
    BBFAdd_18_1.in1 is invalid
    BBFAdd_18_1.in1 <= _T_3260.node @[DspReal.scala 81:21]
    BBFAdd_18_1.in2 <= _T_3279.node @[DspReal.scala 82:21]
    wire _T_3285 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3285 is invalid @[DspReal.scala 83:19]
    _T_3285.node <= BBFAdd_18_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_14_1 of BBFMultiply_14 @[DspReal.scala 106:36]
    BBFMultiply_14_1.out is invalid
    BBFMultiply_14_1.in2 is invalid
    BBFMultiply_14_1.in1 is invalid
    BBFMultiply_14_1.in1 <= stage_outputs_0_7.real.node @[DspReal.scala 81:21]
    BBFMultiply_14_1.in2 <= twiddle[0].imaginary.node @[DspReal.scala 82:21]
    wire _T_3291 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3291 is invalid @[DspReal.scala 83:19]
    _T_3291.node <= BBFMultiply_14_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_15_1 of BBFMultiply_15 @[DspReal.scala 106:36]
    BBFMultiply_15_1.out is invalid
    BBFMultiply_15_1.in2 is invalid
    BBFMultiply_15_1.in1 is invalid
    BBFMultiply_15_1.in1 <= stage_outputs_0_7.imaginary.node @[DspReal.scala 81:21]
    BBFMultiply_15_1.in2 <= twiddle[0].real.node @[DspReal.scala 82:21]
    wire _T_3297 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3297 is invalid @[DspReal.scala 83:19]
    _T_3297.node <= BBFMultiply_15_1.out @[DspReal.scala 84:14]
    inst BBFAdd_19_1 of BBFAdd_19 @[DspReal.scala 98:36]
    BBFAdd_19_1.out is invalid
    BBFAdd_19_1.in2 is invalid
    BBFAdd_19_1.in1 is invalid
    BBFAdd_19_1.in1 <= _T_3291.node @[DspReal.scala 81:21]
    BBFAdd_19_1.in2 <= _T_3297.node @[DspReal.scala 82:21]
    wire _T_3303 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3303 is invalid @[DspReal.scala 83:19]
    _T_3303.node <= BBFAdd_19_1.out @[DspReal.scala 84:14]
    wire _T_3319 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_3319 is invalid @[DspComplex.scala 14:22]
    _T_3319.real.node <= _T_3285.node @[DspComplex.scala 15:17]
    _T_3319.imaginary.node <= _T_3303.node @[DspComplex.scala 16:22]
    inst BBFAdd_20_1 of BBFAdd_20 @[DspReal.scala 98:36]
    BBFAdd_20_1.out is invalid
    BBFAdd_20_1.in2 is invalid
    BBFAdd_20_1.in1 is invalid
    BBFAdd_20_1.in1 <= stage_outputs_0_3.real.node @[DspReal.scala 81:21]
    BBFAdd_20_1.in2 <= _T_3319.real.node @[DspReal.scala 82:21]
    wire _T_3323 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3323 is invalid @[DspReal.scala 83:19]
    _T_3323.node <= BBFAdd_20_1.out @[DspReal.scala 84:14]
    inst BBFAdd_21_1 of BBFAdd_21 @[DspReal.scala 98:36]
    BBFAdd_21_1.out is invalid
    BBFAdd_21_1.in2 is invalid
    BBFAdd_21_1.in1 is invalid
    BBFAdd_21_1.in1 <= stage_outputs_0_3.imaginary.node @[DspReal.scala 81:21]
    BBFAdd_21_1.in2 <= _T_3319.imaginary.node @[DspReal.scala 82:21]
    wire _T_3329 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3329 is invalid @[DspReal.scala 83:19]
    _T_3329.node <= BBFAdd_21_1.out @[DspReal.scala 84:14]
    wire _T_3345 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_3345 is invalid @[DspComplex.scala 14:22]
    _T_3345.real.node <= _T_3323.node @[DspComplex.scala 15:17]
    _T_3345.imaginary.node <= _T_3329.node @[DspComplex.scala 16:22]
    wire _T_3349 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_3349 is invalid @[DspReal.scala 165:19]
    _T_3349.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_17_1 of BBFSubtract_17 @[DspReal.scala 102:36]
    BBFSubtract_17_1.out is invalid
    BBFSubtract_17_1.in2 is invalid
    BBFSubtract_17_1.in1 is invalid
    BBFSubtract_17_1.in1 <= _T_3349.node @[DspReal.scala 81:21]
    BBFSubtract_17_1.in2 <= _T_3319.real.node @[DspReal.scala 82:21]
    wire _T_3356 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3356 is invalid @[DspReal.scala 83:19]
    _T_3356.node <= BBFSubtract_17_1.out @[DspReal.scala 84:14]
    wire _T_3362 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_3362 is invalid @[DspReal.scala 165:19]
    _T_3362.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_18_1 of BBFSubtract_18 @[DspReal.scala 102:36]
    BBFSubtract_18_1.out is invalid
    BBFSubtract_18_1.in2 is invalid
    BBFSubtract_18_1.in1 is invalid
    BBFSubtract_18_1.in1 <= _T_3362.node @[DspReal.scala 81:21]
    BBFSubtract_18_1.in2 <= _T_3319.imaginary.node @[DspReal.scala 82:21]
    wire _T_3369 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3369 is invalid @[DspReal.scala 83:19]
    _T_3369.node <= BBFSubtract_18_1.out @[DspReal.scala 84:14]
    wire _T_3385 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_3385 is invalid @[DspComplex.scala 14:22]
    _T_3385.real.node <= _T_3356.node @[DspComplex.scala 15:17]
    _T_3385.imaginary.node <= _T_3369.node @[DspComplex.scala 16:22]
    inst BBFAdd_22_1 of BBFAdd_22 @[DspReal.scala 98:36]
    BBFAdd_22_1.out is invalid
    BBFAdd_22_1.in2 is invalid
    BBFAdd_22_1.in1 is invalid
    BBFAdd_22_1.in1 <= stage_outputs_0_3.real.node @[DspReal.scala 81:21]
    BBFAdd_22_1.in2 <= _T_3385.real.node @[DspReal.scala 82:21]
    wire _T_3389 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3389 is invalid @[DspReal.scala 83:19]
    _T_3389.node <= BBFAdd_22_1.out @[DspReal.scala 84:14]
    inst BBFAdd_23_1 of BBFAdd_23 @[DspReal.scala 98:36]
    BBFAdd_23_1.out is invalid
    BBFAdd_23_1.in2 is invalid
    BBFAdd_23_1.in1 is invalid
    BBFAdd_23_1.in1 <= stage_outputs_0_3.imaginary.node @[DspReal.scala 81:21]
    BBFAdd_23_1.in2 <= _T_3385.imaginary.node @[DspReal.scala 82:21]
    wire _T_3395 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3395 is invalid @[DspReal.scala 83:19]
    _T_3395.node <= BBFAdd_23_1.out @[DspReal.scala 84:14]
    wire _T_3411 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_3411 is invalid @[DspComplex.scala 14:22]
    _T_3411.real.node <= _T_3389.node @[DspComplex.scala 15:17]
    _T_3411.imaginary.node <= _T_3395.node @[DspComplex.scala 16:22]
    cmem _T_3426 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_3429 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_3437 = _T_3426[UInt<1>("h00")], clock
      _T_3437.imaginary.node <= _T_3345.imaginary.node @[FFTUtilities.scala 172:29]
      _T_3437.real.node <= _T_3345.real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_3445 = _T_3426[UInt<1>("h00")], clock
    stage_outputs_1_3.imaginary.node <= _T_3445.imaginary.node @[FFT.scala 75:14]
    stage_outputs_1_3.real.node <= _T_3445.real.node @[FFT.scala 75:14]
    cmem _T_3460 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_3463 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_3471 = _T_3460[UInt<1>("h00")], clock
      _T_3471.imaginary.node <= _T_3411.imaginary.node @[FFTUtilities.scala 172:29]
      _T_3471.real.node <= _T_3411.real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_3479 = _T_3460[UInt<1>("h00")], clock
    stage_outputs_1_7.imaginary.node <= _T_3479.imaginary.node @[FFT.scala 75:14]
    stage_outputs_1_7.real.node <= _T_3479.real.node @[FFT.scala 75:14]
    cmem _T_3494 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_3497 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_3505 = _T_3494[UInt<1>("h00")], clock
      _T_3505.imaginary.node <= twiddle[1].imaginary.node @[FFTUtilities.scala 172:29]
      _T_3505.real.node <= twiddle[1].real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_3513 = _T_3494[UInt<1>("h00")], clock
    inst BBFMultiply_16_1 of BBFMultiply_16 @[DspReal.scala 106:36]
    BBFMultiply_16_1.out is invalid
    BBFMultiply_16_1.in2 is invalid
    BBFMultiply_16_1.in1 is invalid
    BBFMultiply_16_1.in1 <= stage_outputs_1_2.real.node @[DspReal.scala 81:21]
    BBFMultiply_16_1.in2 <= _T_3513.real.node @[DspReal.scala 82:21]
    wire _T_3517 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3517 is invalid @[DspReal.scala 83:19]
    _T_3517.node <= BBFMultiply_16_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_17_1 of BBFMultiply_17 @[DspReal.scala 106:36]
    BBFMultiply_17_1.out is invalid
    BBFMultiply_17_1.in2 is invalid
    BBFMultiply_17_1.in1 is invalid
    BBFMultiply_17_1.in1 <= stage_outputs_1_2.imaginary.node @[DspReal.scala 81:21]
    BBFMultiply_17_1.in2 <= _T_3513.imaginary.node @[DspReal.scala 82:21]
    wire _T_3523 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3523 is invalid @[DspReal.scala 83:19]
    _T_3523.node <= BBFMultiply_17_1.out @[DspReal.scala 84:14]
    wire _T_3529 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_3529 is invalid @[DspReal.scala 165:19]
    _T_3529.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_19_1 of BBFSubtract_19 @[DspReal.scala 102:36]
    BBFSubtract_19_1.out is invalid
    BBFSubtract_19_1.in2 is invalid
    BBFSubtract_19_1.in1 is invalid
    BBFSubtract_19_1.in1 <= _T_3529.node @[DspReal.scala 81:21]
    BBFSubtract_19_1.in2 <= _T_3523.node @[DspReal.scala 82:21]
    wire _T_3536 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3536 is invalid @[DspReal.scala 83:19]
    _T_3536.node <= BBFSubtract_19_1.out @[DspReal.scala 84:14]
    inst BBFAdd_24_1 of BBFAdd_24 @[DspReal.scala 98:36]
    BBFAdd_24_1.out is invalid
    BBFAdd_24_1.in2 is invalid
    BBFAdd_24_1.in1 is invalid
    BBFAdd_24_1.in1 <= _T_3517.node @[DspReal.scala 81:21]
    BBFAdd_24_1.in2 <= _T_3536.node @[DspReal.scala 82:21]
    wire _T_3542 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3542 is invalid @[DspReal.scala 83:19]
    _T_3542.node <= BBFAdd_24_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_18_1 of BBFMultiply_18 @[DspReal.scala 106:36]
    BBFMultiply_18_1.out is invalid
    BBFMultiply_18_1.in2 is invalid
    BBFMultiply_18_1.in1 is invalid
    BBFMultiply_18_1.in1 <= stage_outputs_1_2.real.node @[DspReal.scala 81:21]
    BBFMultiply_18_1.in2 <= _T_3513.imaginary.node @[DspReal.scala 82:21]
    wire _T_3548 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3548 is invalid @[DspReal.scala 83:19]
    _T_3548.node <= BBFMultiply_18_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_19_1 of BBFMultiply_19 @[DspReal.scala 106:36]
    BBFMultiply_19_1.out is invalid
    BBFMultiply_19_1.in2 is invalid
    BBFMultiply_19_1.in1 is invalid
    BBFMultiply_19_1.in1 <= stage_outputs_1_2.imaginary.node @[DspReal.scala 81:21]
    BBFMultiply_19_1.in2 <= _T_3513.real.node @[DspReal.scala 82:21]
    wire _T_3554 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3554 is invalid @[DspReal.scala 83:19]
    _T_3554.node <= BBFMultiply_19_1.out @[DspReal.scala 84:14]
    inst BBFAdd_25_1 of BBFAdd_25 @[DspReal.scala 98:36]
    BBFAdd_25_1.out is invalid
    BBFAdd_25_1.in2 is invalid
    BBFAdd_25_1.in1 is invalid
    BBFAdd_25_1.in1 <= _T_3548.node @[DspReal.scala 81:21]
    BBFAdd_25_1.in2 <= _T_3554.node @[DspReal.scala 82:21]
    wire _T_3560 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3560 is invalid @[DspReal.scala 83:19]
    _T_3560.node <= BBFAdd_25_1.out @[DspReal.scala 84:14]
    wire _T_3576 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_3576 is invalid @[DspComplex.scala 14:22]
    _T_3576.real.node <= _T_3542.node @[DspComplex.scala 15:17]
    _T_3576.imaginary.node <= _T_3560.node @[DspComplex.scala 16:22]
    inst BBFAdd_26_1 of BBFAdd_26 @[DspReal.scala 98:36]
    BBFAdd_26_1.out is invalid
    BBFAdd_26_1.in2 is invalid
    BBFAdd_26_1.in1 is invalid
    BBFAdd_26_1.in1 <= stage_outputs_1_0.real.node @[DspReal.scala 81:21]
    BBFAdd_26_1.in2 <= _T_3576.real.node @[DspReal.scala 82:21]
    wire _T_3580 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3580 is invalid @[DspReal.scala 83:19]
    _T_3580.node <= BBFAdd_26_1.out @[DspReal.scala 84:14]
    inst BBFAdd_27_1 of BBFAdd_27 @[DspReal.scala 98:36]
    BBFAdd_27_1.out is invalid
    BBFAdd_27_1.in2 is invalid
    BBFAdd_27_1.in1 is invalid
    BBFAdd_27_1.in1 <= stage_outputs_1_0.imaginary.node @[DspReal.scala 81:21]
    BBFAdd_27_1.in2 <= _T_3576.imaginary.node @[DspReal.scala 82:21]
    wire _T_3586 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3586 is invalid @[DspReal.scala 83:19]
    _T_3586.node <= BBFAdd_27_1.out @[DspReal.scala 84:14]
    wire _T_3602 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_3602 is invalid @[DspComplex.scala 14:22]
    _T_3602.real.node <= _T_3580.node @[DspComplex.scala 15:17]
    _T_3602.imaginary.node <= _T_3586.node @[DspComplex.scala 16:22]
    wire _T_3606 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_3606 is invalid @[DspReal.scala 165:19]
    _T_3606.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_20_1 of BBFSubtract_20 @[DspReal.scala 102:36]
    BBFSubtract_20_1.out is invalid
    BBFSubtract_20_1.in2 is invalid
    BBFSubtract_20_1.in1 is invalid
    BBFSubtract_20_1.in1 <= _T_3606.node @[DspReal.scala 81:21]
    BBFSubtract_20_1.in2 <= _T_3576.real.node @[DspReal.scala 82:21]
    wire _T_3613 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3613 is invalid @[DspReal.scala 83:19]
    _T_3613.node <= BBFSubtract_20_1.out @[DspReal.scala 84:14]
    wire _T_3619 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_3619 is invalid @[DspReal.scala 165:19]
    _T_3619.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_21_1 of BBFSubtract_21 @[DspReal.scala 102:36]
    BBFSubtract_21_1.out is invalid
    BBFSubtract_21_1.in2 is invalid
    BBFSubtract_21_1.in1 is invalid
    BBFSubtract_21_1.in1 <= _T_3619.node @[DspReal.scala 81:21]
    BBFSubtract_21_1.in2 <= _T_3576.imaginary.node @[DspReal.scala 82:21]
    wire _T_3626 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3626 is invalid @[DspReal.scala 83:19]
    _T_3626.node <= BBFSubtract_21_1.out @[DspReal.scala 84:14]
    wire _T_3642 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_3642 is invalid @[DspComplex.scala 14:22]
    _T_3642.real.node <= _T_3613.node @[DspComplex.scala 15:17]
    _T_3642.imaginary.node <= _T_3626.node @[DspComplex.scala 16:22]
    inst BBFAdd_28_1 of BBFAdd_28 @[DspReal.scala 98:36]
    BBFAdd_28_1.out is invalid
    BBFAdd_28_1.in2 is invalid
    BBFAdd_28_1.in1 is invalid
    BBFAdd_28_1.in1 <= stage_outputs_1_0.real.node @[DspReal.scala 81:21]
    BBFAdd_28_1.in2 <= _T_3642.real.node @[DspReal.scala 82:21]
    wire _T_3646 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3646 is invalid @[DspReal.scala 83:19]
    _T_3646.node <= BBFAdd_28_1.out @[DspReal.scala 84:14]
    inst BBFAdd_29_1 of BBFAdd_29 @[DspReal.scala 98:36]
    BBFAdd_29_1.out is invalid
    BBFAdd_29_1.in2 is invalid
    BBFAdd_29_1.in1 is invalid
    BBFAdd_29_1.in1 <= stage_outputs_1_0.imaginary.node @[DspReal.scala 81:21]
    BBFAdd_29_1.in2 <= _T_3642.imaginary.node @[DspReal.scala 82:21]
    wire _T_3652 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3652 is invalid @[DspReal.scala 83:19]
    _T_3652.node <= BBFAdd_29_1.out @[DspReal.scala 84:14]
    wire _T_3668 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_3668 is invalid @[DspComplex.scala 14:22]
    _T_3668.real.node <= _T_3646.node @[DspComplex.scala 15:17]
    _T_3668.imaginary.node <= _T_3652.node @[DspComplex.scala 16:22]
    cmem _T_3683 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_3686 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_3694 = _T_3683[UInt<1>("h00")], clock
      _T_3694.imaginary.node <= _T_3602.imaginary.node @[FFTUtilities.scala 172:29]
      _T_3694.real.node <= _T_3602.real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_3702 = _T_3683[UInt<1>("h00")], clock
    stage_outputs_2_0.imaginary.node <= _T_3702.imaginary.node @[FFT.scala 75:14]
    stage_outputs_2_0.real.node <= _T_3702.real.node @[FFT.scala 75:14]
    cmem _T_3717 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_3720 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_3728 = _T_3717[UInt<1>("h00")], clock
      _T_3728.imaginary.node <= _T_3668.imaginary.node @[FFTUtilities.scala 172:29]
      _T_3728.real.node <= _T_3668.real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_3736 = _T_3717[UInt<1>("h00")], clock
    stage_outputs_2_2.imaginary.node <= _T_3736.imaginary.node @[FFT.scala 75:14]
    stage_outputs_2_2.real.node <= _T_3736.real.node @[FFT.scala 75:14]
    cmem _T_3751 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_3754 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_3762 = _T_3751[UInt<1>("h00")], clock
      _T_3762.imaginary.node <= twiddle[1].imaginary.node @[FFTUtilities.scala 172:29]
      _T_3762.real.node <= twiddle[1].real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_3770 = _T_3751[UInt<1>("h00")], clock
    inst BBFMultiply_20_1 of BBFMultiply_20 @[DspReal.scala 106:36]
    BBFMultiply_20_1.out is invalid
    BBFMultiply_20_1.in2 is invalid
    BBFMultiply_20_1.in1 is invalid
    BBFMultiply_20_1.in1 <= stage_outputs_1_3.real.node @[DspReal.scala 81:21]
    BBFMultiply_20_1.in2 <= _T_3770.real.node @[DspReal.scala 82:21]
    wire _T_3774 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3774 is invalid @[DspReal.scala 83:19]
    _T_3774.node <= BBFMultiply_20_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_21_1 of BBFMultiply_21 @[DspReal.scala 106:36]
    BBFMultiply_21_1.out is invalid
    BBFMultiply_21_1.in2 is invalid
    BBFMultiply_21_1.in1 is invalid
    BBFMultiply_21_1.in1 <= stage_outputs_1_3.imaginary.node @[DspReal.scala 81:21]
    BBFMultiply_21_1.in2 <= _T_3770.imaginary.node @[DspReal.scala 82:21]
    wire _T_3780 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3780 is invalid @[DspReal.scala 83:19]
    _T_3780.node <= BBFMultiply_21_1.out @[DspReal.scala 84:14]
    wire _T_3786 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_3786 is invalid @[DspReal.scala 165:19]
    _T_3786.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_22_1 of BBFSubtract_22 @[DspReal.scala 102:36]
    BBFSubtract_22_1.out is invalid
    BBFSubtract_22_1.in2 is invalid
    BBFSubtract_22_1.in1 is invalid
    BBFSubtract_22_1.in1 <= _T_3786.node @[DspReal.scala 81:21]
    BBFSubtract_22_1.in2 <= _T_3780.node @[DspReal.scala 82:21]
    wire _T_3793 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3793 is invalid @[DspReal.scala 83:19]
    _T_3793.node <= BBFSubtract_22_1.out @[DspReal.scala 84:14]
    inst BBFAdd_30_1 of BBFAdd_30 @[DspReal.scala 98:36]
    BBFAdd_30_1.out is invalid
    BBFAdd_30_1.in2 is invalid
    BBFAdd_30_1.in1 is invalid
    BBFAdd_30_1.in1 <= _T_3774.node @[DspReal.scala 81:21]
    BBFAdd_30_1.in2 <= _T_3793.node @[DspReal.scala 82:21]
    wire _T_3799 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3799 is invalid @[DspReal.scala 83:19]
    _T_3799.node <= BBFAdd_30_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_22_1 of BBFMultiply_22 @[DspReal.scala 106:36]
    BBFMultiply_22_1.out is invalid
    BBFMultiply_22_1.in2 is invalid
    BBFMultiply_22_1.in1 is invalid
    BBFMultiply_22_1.in1 <= stage_outputs_1_3.real.node @[DspReal.scala 81:21]
    BBFMultiply_22_1.in2 <= _T_3770.imaginary.node @[DspReal.scala 82:21]
    wire _T_3805 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3805 is invalid @[DspReal.scala 83:19]
    _T_3805.node <= BBFMultiply_22_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_23_1 of BBFMultiply_23 @[DspReal.scala 106:36]
    BBFMultiply_23_1.out is invalid
    BBFMultiply_23_1.in2 is invalid
    BBFMultiply_23_1.in1 is invalid
    BBFMultiply_23_1.in1 <= stage_outputs_1_3.imaginary.node @[DspReal.scala 81:21]
    BBFMultiply_23_1.in2 <= _T_3770.real.node @[DspReal.scala 82:21]
    wire _T_3811 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3811 is invalid @[DspReal.scala 83:19]
    _T_3811.node <= BBFMultiply_23_1.out @[DspReal.scala 84:14]
    inst BBFAdd_31_1 of BBFAdd_31 @[DspReal.scala 98:36]
    BBFAdd_31_1.out is invalid
    BBFAdd_31_1.in2 is invalid
    BBFAdd_31_1.in1 is invalid
    BBFAdd_31_1.in1 <= _T_3805.node @[DspReal.scala 81:21]
    BBFAdd_31_1.in2 <= _T_3811.node @[DspReal.scala 82:21]
    wire _T_3817 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3817 is invalid @[DspReal.scala 83:19]
    _T_3817.node <= BBFAdd_31_1.out @[DspReal.scala 84:14]
    wire _T_3833 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_3833 is invalid @[DspComplex.scala 14:22]
    _T_3833.real.node <= _T_3799.node @[DspComplex.scala 15:17]
    _T_3833.imaginary.node <= _T_3817.node @[DspComplex.scala 16:22]
    inst BBFAdd_32_1 of BBFAdd_32 @[DspReal.scala 98:36]
    BBFAdd_32_1.out is invalid
    BBFAdd_32_1.in2 is invalid
    BBFAdd_32_1.in1 is invalid
    BBFAdd_32_1.in1 <= stage_outputs_1_1.real.node @[DspReal.scala 81:21]
    BBFAdd_32_1.in2 <= _T_3833.real.node @[DspReal.scala 82:21]
    wire _T_3837 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3837 is invalid @[DspReal.scala 83:19]
    _T_3837.node <= BBFAdd_32_1.out @[DspReal.scala 84:14]
    inst BBFAdd_33_1 of BBFAdd_33 @[DspReal.scala 98:36]
    BBFAdd_33_1.out is invalid
    BBFAdd_33_1.in2 is invalid
    BBFAdd_33_1.in1 is invalid
    BBFAdd_33_1.in1 <= stage_outputs_1_1.imaginary.node @[DspReal.scala 81:21]
    BBFAdd_33_1.in2 <= _T_3833.imaginary.node @[DspReal.scala 82:21]
    wire _T_3843 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3843 is invalid @[DspReal.scala 83:19]
    _T_3843.node <= BBFAdd_33_1.out @[DspReal.scala 84:14]
    wire _T_3859 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_3859 is invalid @[DspComplex.scala 14:22]
    _T_3859.real.node <= _T_3837.node @[DspComplex.scala 15:17]
    _T_3859.imaginary.node <= _T_3843.node @[DspComplex.scala 16:22]
    wire _T_3863 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_3863 is invalid @[DspReal.scala 165:19]
    _T_3863.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_23_1 of BBFSubtract_23 @[DspReal.scala 102:36]
    BBFSubtract_23_1.out is invalid
    BBFSubtract_23_1.in2 is invalid
    BBFSubtract_23_1.in1 is invalid
    BBFSubtract_23_1.in1 <= _T_3863.node @[DspReal.scala 81:21]
    BBFSubtract_23_1.in2 <= _T_3833.real.node @[DspReal.scala 82:21]
    wire _T_3870 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3870 is invalid @[DspReal.scala 83:19]
    _T_3870.node <= BBFSubtract_23_1.out @[DspReal.scala 84:14]
    wire _T_3876 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_3876 is invalid @[DspReal.scala 165:19]
    _T_3876.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_24_1 of BBFSubtract_24 @[DspReal.scala 102:36]
    BBFSubtract_24_1.out is invalid
    BBFSubtract_24_1.in2 is invalid
    BBFSubtract_24_1.in1 is invalid
    BBFSubtract_24_1.in1 <= _T_3876.node @[DspReal.scala 81:21]
    BBFSubtract_24_1.in2 <= _T_3833.imaginary.node @[DspReal.scala 82:21]
    wire _T_3883 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3883 is invalid @[DspReal.scala 83:19]
    _T_3883.node <= BBFSubtract_24_1.out @[DspReal.scala 84:14]
    wire _T_3899 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_3899 is invalid @[DspComplex.scala 14:22]
    _T_3899.real.node <= _T_3870.node @[DspComplex.scala 15:17]
    _T_3899.imaginary.node <= _T_3883.node @[DspComplex.scala 16:22]
    inst BBFAdd_34_1 of BBFAdd_34 @[DspReal.scala 98:36]
    BBFAdd_34_1.out is invalid
    BBFAdd_34_1.in2 is invalid
    BBFAdd_34_1.in1 is invalid
    BBFAdd_34_1.in1 <= stage_outputs_1_1.real.node @[DspReal.scala 81:21]
    BBFAdd_34_1.in2 <= _T_3899.real.node @[DspReal.scala 82:21]
    wire _T_3903 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3903 is invalid @[DspReal.scala 83:19]
    _T_3903.node <= BBFAdd_34_1.out @[DspReal.scala 84:14]
    inst BBFAdd_35_1 of BBFAdd_35 @[DspReal.scala 98:36]
    BBFAdd_35_1.out is invalid
    BBFAdd_35_1.in2 is invalid
    BBFAdd_35_1.in1 is invalid
    BBFAdd_35_1.in1 <= stage_outputs_1_1.imaginary.node @[DspReal.scala 81:21]
    BBFAdd_35_1.in2 <= _T_3899.imaginary.node @[DspReal.scala 82:21]
    wire _T_3909 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3909 is invalid @[DspReal.scala 83:19]
    _T_3909.node <= BBFAdd_35_1.out @[DspReal.scala 84:14]
    wire _T_3925 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_3925 is invalid @[DspComplex.scala 14:22]
    _T_3925.real.node <= _T_3903.node @[DspComplex.scala 15:17]
    _T_3925.imaginary.node <= _T_3909.node @[DspComplex.scala 16:22]
    cmem _T_3940 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_3943 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_3951 = _T_3940[UInt<1>("h00")], clock
      _T_3951.imaginary.node <= _T_3859.imaginary.node @[FFTUtilities.scala 172:29]
      _T_3951.real.node <= _T_3859.real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_3959 = _T_3940[UInt<1>("h00")], clock
    stage_outputs_2_1.imaginary.node <= _T_3959.imaginary.node @[FFT.scala 75:14]
    stage_outputs_2_1.real.node <= _T_3959.real.node @[FFT.scala 75:14]
    cmem _T_3974 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_3977 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_3985 = _T_3974[UInt<1>("h00")], clock
      _T_3985.imaginary.node <= _T_3925.imaginary.node @[FFTUtilities.scala 172:29]
      _T_3985.real.node <= _T_3925.real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_3993 = _T_3974[UInt<1>("h00")], clock
    stage_outputs_2_3.imaginary.node <= _T_3993.imaginary.node @[FFT.scala 75:14]
    stage_outputs_2_3.real.node <= _T_3993.real.node @[FFT.scala 75:14]
    cmem _T_4008 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_4011 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_4019 = _T_4008[UInt<1>("h00")], clock
      _T_4019.imaginary.node <= twiddle[4].imaginary.node @[FFTUtilities.scala 172:29]
      _T_4019.real.node <= twiddle[4].real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_4027 = _T_4008[UInt<1>("h00")], clock
    inst BBFMultiply_24_1 of BBFMultiply_24 @[DspReal.scala 106:36]
    BBFMultiply_24_1.out is invalid
    BBFMultiply_24_1.in2 is invalid
    BBFMultiply_24_1.in1 is invalid
    BBFMultiply_24_1.in1 <= stage_outputs_1_6.real.node @[DspReal.scala 81:21]
    BBFMultiply_24_1.in2 <= _T_4027.real.node @[DspReal.scala 82:21]
    wire _T_4031 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4031 is invalid @[DspReal.scala 83:19]
    _T_4031.node <= BBFMultiply_24_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_25_1 of BBFMultiply_25 @[DspReal.scala 106:36]
    BBFMultiply_25_1.out is invalid
    BBFMultiply_25_1.in2 is invalid
    BBFMultiply_25_1.in1 is invalid
    BBFMultiply_25_1.in1 <= stage_outputs_1_6.imaginary.node @[DspReal.scala 81:21]
    BBFMultiply_25_1.in2 <= _T_4027.imaginary.node @[DspReal.scala 82:21]
    wire _T_4037 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4037 is invalid @[DspReal.scala 83:19]
    _T_4037.node <= BBFMultiply_25_1.out @[DspReal.scala 84:14]
    wire _T_4043 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_4043 is invalid @[DspReal.scala 165:19]
    _T_4043.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_25_1 of BBFSubtract_25 @[DspReal.scala 102:36]
    BBFSubtract_25_1.out is invalid
    BBFSubtract_25_1.in2 is invalid
    BBFSubtract_25_1.in1 is invalid
    BBFSubtract_25_1.in1 <= _T_4043.node @[DspReal.scala 81:21]
    BBFSubtract_25_1.in2 <= _T_4037.node @[DspReal.scala 82:21]
    wire _T_4050 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4050 is invalid @[DspReal.scala 83:19]
    _T_4050.node <= BBFSubtract_25_1.out @[DspReal.scala 84:14]
    inst BBFAdd_36_1 of BBFAdd_36 @[DspReal.scala 98:36]
    BBFAdd_36_1.out is invalid
    BBFAdd_36_1.in2 is invalid
    BBFAdd_36_1.in1 is invalid
    BBFAdd_36_1.in1 <= _T_4031.node @[DspReal.scala 81:21]
    BBFAdd_36_1.in2 <= _T_4050.node @[DspReal.scala 82:21]
    wire _T_4056 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4056 is invalid @[DspReal.scala 83:19]
    _T_4056.node <= BBFAdd_36_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_26_1 of BBFMultiply_26 @[DspReal.scala 106:36]
    BBFMultiply_26_1.out is invalid
    BBFMultiply_26_1.in2 is invalid
    BBFMultiply_26_1.in1 is invalid
    BBFMultiply_26_1.in1 <= stage_outputs_1_6.real.node @[DspReal.scala 81:21]
    BBFMultiply_26_1.in2 <= _T_4027.imaginary.node @[DspReal.scala 82:21]
    wire _T_4062 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4062 is invalid @[DspReal.scala 83:19]
    _T_4062.node <= BBFMultiply_26_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_27_1 of BBFMultiply_27 @[DspReal.scala 106:36]
    BBFMultiply_27_1.out is invalid
    BBFMultiply_27_1.in2 is invalid
    BBFMultiply_27_1.in1 is invalid
    BBFMultiply_27_1.in1 <= stage_outputs_1_6.imaginary.node @[DspReal.scala 81:21]
    BBFMultiply_27_1.in2 <= _T_4027.real.node @[DspReal.scala 82:21]
    wire _T_4068 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4068 is invalid @[DspReal.scala 83:19]
    _T_4068.node <= BBFMultiply_27_1.out @[DspReal.scala 84:14]
    inst BBFAdd_37_1 of BBFAdd_37 @[DspReal.scala 98:36]
    BBFAdd_37_1.out is invalid
    BBFAdd_37_1.in2 is invalid
    BBFAdd_37_1.in1 is invalid
    BBFAdd_37_1.in1 <= _T_4062.node @[DspReal.scala 81:21]
    BBFAdd_37_1.in2 <= _T_4068.node @[DspReal.scala 82:21]
    wire _T_4074 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4074 is invalid @[DspReal.scala 83:19]
    _T_4074.node <= BBFAdd_37_1.out @[DspReal.scala 84:14]
    wire _T_4090 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_4090 is invalid @[DspComplex.scala 14:22]
    _T_4090.real.node <= _T_4056.node @[DspComplex.scala 15:17]
    _T_4090.imaginary.node <= _T_4074.node @[DspComplex.scala 16:22]
    inst BBFAdd_38_1 of BBFAdd_38 @[DspReal.scala 98:36]
    BBFAdd_38_1.out is invalid
    BBFAdd_38_1.in2 is invalid
    BBFAdd_38_1.in1 is invalid
    BBFAdd_38_1.in1 <= stage_outputs_1_4.real.node @[DspReal.scala 81:21]
    BBFAdd_38_1.in2 <= _T_4090.real.node @[DspReal.scala 82:21]
    wire _T_4094 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4094 is invalid @[DspReal.scala 83:19]
    _T_4094.node <= BBFAdd_38_1.out @[DspReal.scala 84:14]
    inst BBFAdd_39_1 of BBFAdd_39 @[DspReal.scala 98:36]
    BBFAdd_39_1.out is invalid
    BBFAdd_39_1.in2 is invalid
    BBFAdd_39_1.in1 is invalid
    BBFAdd_39_1.in1 <= stage_outputs_1_4.imaginary.node @[DspReal.scala 81:21]
    BBFAdd_39_1.in2 <= _T_4090.imaginary.node @[DspReal.scala 82:21]
    wire _T_4100 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4100 is invalid @[DspReal.scala 83:19]
    _T_4100.node <= BBFAdd_39_1.out @[DspReal.scala 84:14]
    wire _T_4116 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_4116 is invalid @[DspComplex.scala 14:22]
    _T_4116.real.node <= _T_4094.node @[DspComplex.scala 15:17]
    _T_4116.imaginary.node <= _T_4100.node @[DspComplex.scala 16:22]
    wire _T_4120 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_4120 is invalid @[DspReal.scala 165:19]
    _T_4120.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_26_1 of BBFSubtract_26 @[DspReal.scala 102:36]
    BBFSubtract_26_1.out is invalid
    BBFSubtract_26_1.in2 is invalid
    BBFSubtract_26_1.in1 is invalid
    BBFSubtract_26_1.in1 <= _T_4120.node @[DspReal.scala 81:21]
    BBFSubtract_26_1.in2 <= _T_4090.real.node @[DspReal.scala 82:21]
    wire _T_4127 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4127 is invalid @[DspReal.scala 83:19]
    _T_4127.node <= BBFSubtract_26_1.out @[DspReal.scala 84:14]
    wire _T_4133 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_4133 is invalid @[DspReal.scala 165:19]
    _T_4133.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_27_1 of BBFSubtract_27 @[DspReal.scala 102:36]
    BBFSubtract_27_1.out is invalid
    BBFSubtract_27_1.in2 is invalid
    BBFSubtract_27_1.in1 is invalid
    BBFSubtract_27_1.in1 <= _T_4133.node @[DspReal.scala 81:21]
    BBFSubtract_27_1.in2 <= _T_4090.imaginary.node @[DspReal.scala 82:21]
    wire _T_4140 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4140 is invalid @[DspReal.scala 83:19]
    _T_4140.node <= BBFSubtract_27_1.out @[DspReal.scala 84:14]
    wire _T_4156 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_4156 is invalid @[DspComplex.scala 14:22]
    _T_4156.real.node <= _T_4127.node @[DspComplex.scala 15:17]
    _T_4156.imaginary.node <= _T_4140.node @[DspComplex.scala 16:22]
    inst BBFAdd_40_1 of BBFAdd_40 @[DspReal.scala 98:36]
    BBFAdd_40_1.out is invalid
    BBFAdd_40_1.in2 is invalid
    BBFAdd_40_1.in1 is invalid
    BBFAdd_40_1.in1 <= stage_outputs_1_4.real.node @[DspReal.scala 81:21]
    BBFAdd_40_1.in2 <= _T_4156.real.node @[DspReal.scala 82:21]
    wire _T_4160 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4160 is invalid @[DspReal.scala 83:19]
    _T_4160.node <= BBFAdd_40_1.out @[DspReal.scala 84:14]
    inst BBFAdd_41_1 of BBFAdd_41 @[DspReal.scala 98:36]
    BBFAdd_41_1.out is invalid
    BBFAdd_41_1.in2 is invalid
    BBFAdd_41_1.in1 is invalid
    BBFAdd_41_1.in1 <= stage_outputs_1_4.imaginary.node @[DspReal.scala 81:21]
    BBFAdd_41_1.in2 <= _T_4156.imaginary.node @[DspReal.scala 82:21]
    wire _T_4166 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4166 is invalid @[DspReal.scala 83:19]
    _T_4166.node <= BBFAdd_41_1.out @[DspReal.scala 84:14]
    wire _T_4182 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_4182 is invalid @[DspComplex.scala 14:22]
    _T_4182.real.node <= _T_4160.node @[DspComplex.scala 15:17]
    _T_4182.imaginary.node <= _T_4166.node @[DspComplex.scala 16:22]
    cmem _T_4197 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_4200 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_4208 = _T_4197[UInt<1>("h00")], clock
      _T_4208.imaginary.node <= _T_4116.imaginary.node @[FFTUtilities.scala 172:29]
      _T_4208.real.node <= _T_4116.real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_4216 = _T_4197[UInt<1>("h00")], clock
    stage_outputs_2_4.imaginary.node <= _T_4216.imaginary.node @[FFT.scala 75:14]
    stage_outputs_2_4.real.node <= _T_4216.real.node @[FFT.scala 75:14]
    cmem _T_4231 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_4234 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_4242 = _T_4231[UInt<1>("h00")], clock
      _T_4242.imaginary.node <= _T_4182.imaginary.node @[FFTUtilities.scala 172:29]
      _T_4242.real.node <= _T_4182.real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_4250 = _T_4231[UInt<1>("h00")], clock
    stage_outputs_2_6.imaginary.node <= _T_4250.imaginary.node @[FFT.scala 75:14]
    stage_outputs_2_6.real.node <= _T_4250.real.node @[FFT.scala 75:14]
    cmem _T_4265 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_4268 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_4276 = _T_4265[UInt<1>("h00")], clock
      _T_4276.imaginary.node <= twiddle[4].imaginary.node @[FFTUtilities.scala 172:29]
      _T_4276.real.node <= twiddle[4].real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_4284 = _T_4265[UInt<1>("h00")], clock
    inst BBFMultiply_28_1 of BBFMultiply_28 @[DspReal.scala 106:36]
    BBFMultiply_28_1.out is invalid
    BBFMultiply_28_1.in2 is invalid
    BBFMultiply_28_1.in1 is invalid
    BBFMultiply_28_1.in1 <= stage_outputs_1_7.real.node @[DspReal.scala 81:21]
    BBFMultiply_28_1.in2 <= _T_4284.real.node @[DspReal.scala 82:21]
    wire _T_4288 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4288 is invalid @[DspReal.scala 83:19]
    _T_4288.node <= BBFMultiply_28_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_29_1 of BBFMultiply_29 @[DspReal.scala 106:36]
    BBFMultiply_29_1.out is invalid
    BBFMultiply_29_1.in2 is invalid
    BBFMultiply_29_1.in1 is invalid
    BBFMultiply_29_1.in1 <= stage_outputs_1_7.imaginary.node @[DspReal.scala 81:21]
    BBFMultiply_29_1.in2 <= _T_4284.imaginary.node @[DspReal.scala 82:21]
    wire _T_4294 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4294 is invalid @[DspReal.scala 83:19]
    _T_4294.node <= BBFMultiply_29_1.out @[DspReal.scala 84:14]
    wire _T_4300 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_4300 is invalid @[DspReal.scala 165:19]
    _T_4300.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_28_1 of BBFSubtract_28 @[DspReal.scala 102:36]
    BBFSubtract_28_1.out is invalid
    BBFSubtract_28_1.in2 is invalid
    BBFSubtract_28_1.in1 is invalid
    BBFSubtract_28_1.in1 <= _T_4300.node @[DspReal.scala 81:21]
    BBFSubtract_28_1.in2 <= _T_4294.node @[DspReal.scala 82:21]
    wire _T_4307 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4307 is invalid @[DspReal.scala 83:19]
    _T_4307.node <= BBFSubtract_28_1.out @[DspReal.scala 84:14]
    inst BBFAdd_42_1 of BBFAdd_42 @[DspReal.scala 98:36]
    BBFAdd_42_1.out is invalid
    BBFAdd_42_1.in2 is invalid
    BBFAdd_42_1.in1 is invalid
    BBFAdd_42_1.in1 <= _T_4288.node @[DspReal.scala 81:21]
    BBFAdd_42_1.in2 <= _T_4307.node @[DspReal.scala 82:21]
    wire _T_4313 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4313 is invalid @[DspReal.scala 83:19]
    _T_4313.node <= BBFAdd_42_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_30_1 of BBFMultiply_30 @[DspReal.scala 106:36]
    BBFMultiply_30_1.out is invalid
    BBFMultiply_30_1.in2 is invalid
    BBFMultiply_30_1.in1 is invalid
    BBFMultiply_30_1.in1 <= stage_outputs_1_7.real.node @[DspReal.scala 81:21]
    BBFMultiply_30_1.in2 <= _T_4284.imaginary.node @[DspReal.scala 82:21]
    wire _T_4319 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4319 is invalid @[DspReal.scala 83:19]
    _T_4319.node <= BBFMultiply_30_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_31_1 of BBFMultiply_31 @[DspReal.scala 106:36]
    BBFMultiply_31_1.out is invalid
    BBFMultiply_31_1.in2 is invalid
    BBFMultiply_31_1.in1 is invalid
    BBFMultiply_31_1.in1 <= stage_outputs_1_7.imaginary.node @[DspReal.scala 81:21]
    BBFMultiply_31_1.in2 <= _T_4284.real.node @[DspReal.scala 82:21]
    wire _T_4325 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4325 is invalid @[DspReal.scala 83:19]
    _T_4325.node <= BBFMultiply_31_1.out @[DspReal.scala 84:14]
    inst BBFAdd_43_1 of BBFAdd_43 @[DspReal.scala 98:36]
    BBFAdd_43_1.out is invalid
    BBFAdd_43_1.in2 is invalid
    BBFAdd_43_1.in1 is invalid
    BBFAdd_43_1.in1 <= _T_4319.node @[DspReal.scala 81:21]
    BBFAdd_43_1.in2 <= _T_4325.node @[DspReal.scala 82:21]
    wire _T_4331 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4331 is invalid @[DspReal.scala 83:19]
    _T_4331.node <= BBFAdd_43_1.out @[DspReal.scala 84:14]
    wire _T_4347 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_4347 is invalid @[DspComplex.scala 14:22]
    _T_4347.real.node <= _T_4313.node @[DspComplex.scala 15:17]
    _T_4347.imaginary.node <= _T_4331.node @[DspComplex.scala 16:22]
    inst BBFAdd_44_1 of BBFAdd_44 @[DspReal.scala 98:36]
    BBFAdd_44_1.out is invalid
    BBFAdd_44_1.in2 is invalid
    BBFAdd_44_1.in1 is invalid
    BBFAdd_44_1.in1 <= stage_outputs_1_5.real.node @[DspReal.scala 81:21]
    BBFAdd_44_1.in2 <= _T_4347.real.node @[DspReal.scala 82:21]
    wire _T_4351 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4351 is invalid @[DspReal.scala 83:19]
    _T_4351.node <= BBFAdd_44_1.out @[DspReal.scala 84:14]
    inst BBFAdd_45_1 of BBFAdd_45 @[DspReal.scala 98:36]
    BBFAdd_45_1.out is invalid
    BBFAdd_45_1.in2 is invalid
    BBFAdd_45_1.in1 is invalid
    BBFAdd_45_1.in1 <= stage_outputs_1_5.imaginary.node @[DspReal.scala 81:21]
    BBFAdd_45_1.in2 <= _T_4347.imaginary.node @[DspReal.scala 82:21]
    wire _T_4357 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4357 is invalid @[DspReal.scala 83:19]
    _T_4357.node <= BBFAdd_45_1.out @[DspReal.scala 84:14]
    wire _T_4373 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_4373 is invalid @[DspComplex.scala 14:22]
    _T_4373.real.node <= _T_4351.node @[DspComplex.scala 15:17]
    _T_4373.imaginary.node <= _T_4357.node @[DspComplex.scala 16:22]
    wire _T_4377 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_4377 is invalid @[DspReal.scala 165:19]
    _T_4377.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_29_1 of BBFSubtract_29 @[DspReal.scala 102:36]
    BBFSubtract_29_1.out is invalid
    BBFSubtract_29_1.in2 is invalid
    BBFSubtract_29_1.in1 is invalid
    BBFSubtract_29_1.in1 <= _T_4377.node @[DspReal.scala 81:21]
    BBFSubtract_29_1.in2 <= _T_4347.real.node @[DspReal.scala 82:21]
    wire _T_4384 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4384 is invalid @[DspReal.scala 83:19]
    _T_4384.node <= BBFSubtract_29_1.out @[DspReal.scala 84:14]
    wire _T_4390 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_4390 is invalid @[DspReal.scala 165:19]
    _T_4390.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_30_1 of BBFSubtract_30 @[DspReal.scala 102:36]
    BBFSubtract_30_1.out is invalid
    BBFSubtract_30_1.in2 is invalid
    BBFSubtract_30_1.in1 is invalid
    BBFSubtract_30_1.in1 <= _T_4390.node @[DspReal.scala 81:21]
    BBFSubtract_30_1.in2 <= _T_4347.imaginary.node @[DspReal.scala 82:21]
    wire _T_4397 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4397 is invalid @[DspReal.scala 83:19]
    _T_4397.node <= BBFSubtract_30_1.out @[DspReal.scala 84:14]
    wire _T_4413 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_4413 is invalid @[DspComplex.scala 14:22]
    _T_4413.real.node <= _T_4384.node @[DspComplex.scala 15:17]
    _T_4413.imaginary.node <= _T_4397.node @[DspComplex.scala 16:22]
    inst BBFAdd_46_1 of BBFAdd_46 @[DspReal.scala 98:36]
    BBFAdd_46_1.out is invalid
    BBFAdd_46_1.in2 is invalid
    BBFAdd_46_1.in1 is invalid
    BBFAdd_46_1.in1 <= stage_outputs_1_5.real.node @[DspReal.scala 81:21]
    BBFAdd_46_1.in2 <= _T_4413.real.node @[DspReal.scala 82:21]
    wire _T_4417 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4417 is invalid @[DspReal.scala 83:19]
    _T_4417.node <= BBFAdd_46_1.out @[DspReal.scala 84:14]
    inst BBFAdd_47_1 of BBFAdd_47 @[DspReal.scala 98:36]
    BBFAdd_47_1.out is invalid
    BBFAdd_47_1.in2 is invalid
    BBFAdd_47_1.in1 is invalid
    BBFAdd_47_1.in1 <= stage_outputs_1_5.imaginary.node @[DspReal.scala 81:21]
    BBFAdd_47_1.in2 <= _T_4413.imaginary.node @[DspReal.scala 82:21]
    wire _T_4423 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4423 is invalid @[DspReal.scala 83:19]
    _T_4423.node <= BBFAdd_47_1.out @[DspReal.scala 84:14]
    wire _T_4439 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_4439 is invalid @[DspComplex.scala 14:22]
    _T_4439.real.node <= _T_4417.node @[DspComplex.scala 15:17]
    _T_4439.imaginary.node <= _T_4423.node @[DspComplex.scala 16:22]
    cmem _T_4454 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_4457 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_4465 = _T_4454[UInt<1>("h00")], clock
      _T_4465.imaginary.node <= _T_4373.imaginary.node @[FFTUtilities.scala 172:29]
      _T_4465.real.node <= _T_4373.real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_4473 = _T_4454[UInt<1>("h00")], clock
    stage_outputs_2_5.imaginary.node <= _T_4473.imaginary.node @[FFT.scala 75:14]
    stage_outputs_2_5.real.node <= _T_4473.real.node @[FFT.scala 75:14]
    cmem _T_4488 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_4491 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_4499 = _T_4488[UInt<1>("h00")], clock
      _T_4499.imaginary.node <= _T_4439.imaginary.node @[FFTUtilities.scala 172:29]
      _T_4499.real.node <= _T_4439.real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_4507 = _T_4488[UInt<1>("h00")], clock
    stage_outputs_2_7.imaginary.node <= _T_4507.imaginary.node @[FFT.scala 75:14]
    stage_outputs_2_7.real.node <= _T_4507.real.node @[FFT.scala 75:14]
    cmem _T_4522 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[2] @[FFTUtilities.scala 169:21]
    reg _T_4524 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 15:29]
    when io.in.valid : @[Counter.scala 59:17]
      node _T_4526 = eq(_T_4524, UInt<1>("h01")) @[Counter.scala 23:24]
      node _T_4528 = add(_T_4524, UInt<1>("h01")) @[Counter.scala 24:22]
      node _T_4529 = tail(_T_4528, 1) @[Counter.scala 24:22]
      _T_4524 <= _T_4529 @[Counter.scala 24:13]
      skip @[Counter.scala 59:17]
    node _T_4530 = and(io.in.valid, _T_4526) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_4537 = _T_4522[_T_4524], clock
      _T_4537.imaginary.node <= twiddle[2].imaginary.node @[FFTUtilities.scala 172:29]
      _T_4537.real.node <= twiddle[2].real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_4544 = _T_4522[_T_4524], clock
    inst BBFMultiply_32_1 of BBFMultiply_32 @[DspReal.scala 106:36]
    BBFMultiply_32_1.out is invalid
    BBFMultiply_32_1.in2 is invalid
    BBFMultiply_32_1.in1 is invalid
    BBFMultiply_32_1.in1 <= stage_outputs_2_1.real.node @[DspReal.scala 81:21]
    BBFMultiply_32_1.in2 <= _T_4544.real.node @[DspReal.scala 82:21]
    wire _T_4548 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4548 is invalid @[DspReal.scala 83:19]
    _T_4548.node <= BBFMultiply_32_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_33_1 of BBFMultiply_33 @[DspReal.scala 106:36]
    BBFMultiply_33_1.out is invalid
    BBFMultiply_33_1.in2 is invalid
    BBFMultiply_33_1.in1 is invalid
    BBFMultiply_33_1.in1 <= stage_outputs_2_1.imaginary.node @[DspReal.scala 81:21]
    BBFMultiply_33_1.in2 <= _T_4544.imaginary.node @[DspReal.scala 82:21]
    wire _T_4554 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4554 is invalid @[DspReal.scala 83:19]
    _T_4554.node <= BBFMultiply_33_1.out @[DspReal.scala 84:14]
    wire _T_4560 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_4560 is invalid @[DspReal.scala 165:19]
    _T_4560.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_31_1 of BBFSubtract_31 @[DspReal.scala 102:36]
    BBFSubtract_31_1.out is invalid
    BBFSubtract_31_1.in2 is invalid
    BBFSubtract_31_1.in1 is invalid
    BBFSubtract_31_1.in1 <= _T_4560.node @[DspReal.scala 81:21]
    BBFSubtract_31_1.in2 <= _T_4554.node @[DspReal.scala 82:21]
    wire _T_4567 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4567 is invalid @[DspReal.scala 83:19]
    _T_4567.node <= BBFSubtract_31_1.out @[DspReal.scala 84:14]
    inst BBFAdd_48_1 of BBFAdd_48 @[DspReal.scala 98:36]
    BBFAdd_48_1.out is invalid
    BBFAdd_48_1.in2 is invalid
    BBFAdd_48_1.in1 is invalid
    BBFAdd_48_1.in1 <= _T_4548.node @[DspReal.scala 81:21]
    BBFAdd_48_1.in2 <= _T_4567.node @[DspReal.scala 82:21]
    wire _T_4573 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4573 is invalid @[DspReal.scala 83:19]
    _T_4573.node <= BBFAdd_48_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_34_1 of BBFMultiply_34 @[DspReal.scala 106:36]
    BBFMultiply_34_1.out is invalid
    BBFMultiply_34_1.in2 is invalid
    BBFMultiply_34_1.in1 is invalid
    BBFMultiply_34_1.in1 <= stage_outputs_2_1.real.node @[DspReal.scala 81:21]
    BBFMultiply_34_1.in2 <= _T_4544.imaginary.node @[DspReal.scala 82:21]
    wire _T_4579 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4579 is invalid @[DspReal.scala 83:19]
    _T_4579.node <= BBFMultiply_34_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_35_1 of BBFMultiply_35 @[DspReal.scala 106:36]
    BBFMultiply_35_1.out is invalid
    BBFMultiply_35_1.in2 is invalid
    BBFMultiply_35_1.in1 is invalid
    BBFMultiply_35_1.in1 <= stage_outputs_2_1.imaginary.node @[DspReal.scala 81:21]
    BBFMultiply_35_1.in2 <= _T_4544.real.node @[DspReal.scala 82:21]
    wire _T_4585 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4585 is invalid @[DspReal.scala 83:19]
    _T_4585.node <= BBFMultiply_35_1.out @[DspReal.scala 84:14]
    inst BBFAdd_49_1 of BBFAdd_49 @[DspReal.scala 98:36]
    BBFAdd_49_1.out is invalid
    BBFAdd_49_1.in2 is invalid
    BBFAdd_49_1.in1 is invalid
    BBFAdd_49_1.in1 <= _T_4579.node @[DspReal.scala 81:21]
    BBFAdd_49_1.in2 <= _T_4585.node @[DspReal.scala 82:21]
    wire _T_4591 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4591 is invalid @[DspReal.scala 83:19]
    _T_4591.node <= BBFAdd_49_1.out @[DspReal.scala 84:14]
    wire _T_4607 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_4607 is invalid @[DspComplex.scala 14:22]
    _T_4607.real.node <= _T_4573.node @[DspComplex.scala 15:17]
    _T_4607.imaginary.node <= _T_4591.node @[DspComplex.scala 16:22]
    inst BBFAdd_50_1 of BBFAdd_50 @[DspReal.scala 98:36]
    BBFAdd_50_1.out is invalid
    BBFAdd_50_1.in2 is invalid
    BBFAdd_50_1.in1 is invalid
    BBFAdd_50_1.in1 <= stage_outputs_2_0.real.node @[DspReal.scala 81:21]
    BBFAdd_50_1.in2 <= _T_4607.real.node @[DspReal.scala 82:21]
    wire _T_4611 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4611 is invalid @[DspReal.scala 83:19]
    _T_4611.node <= BBFAdd_50_1.out @[DspReal.scala 84:14]
    inst BBFAdd_51_1 of BBFAdd_51 @[DspReal.scala 98:36]
    BBFAdd_51_1.out is invalid
    BBFAdd_51_1.in2 is invalid
    BBFAdd_51_1.in1 is invalid
    BBFAdd_51_1.in1 <= stage_outputs_2_0.imaginary.node @[DspReal.scala 81:21]
    BBFAdd_51_1.in2 <= _T_4607.imaginary.node @[DspReal.scala 82:21]
    wire _T_4617 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4617 is invalid @[DspReal.scala 83:19]
    _T_4617.node <= BBFAdd_51_1.out @[DspReal.scala 84:14]
    wire _T_4633 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_4633 is invalid @[DspComplex.scala 14:22]
    _T_4633.real.node <= _T_4611.node @[DspComplex.scala 15:17]
    _T_4633.imaginary.node <= _T_4617.node @[DspComplex.scala 16:22]
    wire _T_4637 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_4637 is invalid @[DspReal.scala 165:19]
    _T_4637.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_32_1 of BBFSubtract_32 @[DspReal.scala 102:36]
    BBFSubtract_32_1.out is invalid
    BBFSubtract_32_1.in2 is invalid
    BBFSubtract_32_1.in1 is invalid
    BBFSubtract_32_1.in1 <= _T_4637.node @[DspReal.scala 81:21]
    BBFSubtract_32_1.in2 <= _T_4607.real.node @[DspReal.scala 82:21]
    wire _T_4644 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4644 is invalid @[DspReal.scala 83:19]
    _T_4644.node <= BBFSubtract_32_1.out @[DspReal.scala 84:14]
    wire _T_4650 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_4650 is invalid @[DspReal.scala 165:19]
    _T_4650.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_33_1 of BBFSubtract_33 @[DspReal.scala 102:36]
    BBFSubtract_33_1.out is invalid
    BBFSubtract_33_1.in2 is invalid
    BBFSubtract_33_1.in1 is invalid
    BBFSubtract_33_1.in1 <= _T_4650.node @[DspReal.scala 81:21]
    BBFSubtract_33_1.in2 <= _T_4607.imaginary.node @[DspReal.scala 82:21]
    wire _T_4657 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4657 is invalid @[DspReal.scala 83:19]
    _T_4657.node <= BBFSubtract_33_1.out @[DspReal.scala 84:14]
    wire _T_4673 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_4673 is invalid @[DspComplex.scala 14:22]
    _T_4673.real.node <= _T_4644.node @[DspComplex.scala 15:17]
    _T_4673.imaginary.node <= _T_4657.node @[DspComplex.scala 16:22]
    inst BBFAdd_52_1 of BBFAdd_52 @[DspReal.scala 98:36]
    BBFAdd_52_1.out is invalid
    BBFAdd_52_1.in2 is invalid
    BBFAdd_52_1.in1 is invalid
    BBFAdd_52_1.in1 <= stage_outputs_2_0.real.node @[DspReal.scala 81:21]
    BBFAdd_52_1.in2 <= _T_4673.real.node @[DspReal.scala 82:21]
    wire _T_4677 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4677 is invalid @[DspReal.scala 83:19]
    _T_4677.node <= BBFAdd_52_1.out @[DspReal.scala 84:14]
    inst BBFAdd_53_1 of BBFAdd_53 @[DspReal.scala 98:36]
    BBFAdd_53_1.out is invalid
    BBFAdd_53_1.in2 is invalid
    BBFAdd_53_1.in1 is invalid
    BBFAdd_53_1.in1 <= stage_outputs_2_0.imaginary.node @[DspReal.scala 81:21]
    BBFAdd_53_1.in2 <= _T_4673.imaginary.node @[DspReal.scala 82:21]
    wire _T_4683 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4683 is invalid @[DspReal.scala 83:19]
    _T_4683.node <= BBFAdd_53_1.out @[DspReal.scala 84:14]
    wire _T_4699 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_4699 is invalid @[DspComplex.scala 14:22]
    _T_4699.real.node <= _T_4677.node @[DspComplex.scala 15:17]
    _T_4699.imaginary.node <= _T_4683.node @[DspComplex.scala 16:22]
    stage_outputs_3_0.imaginary.node <= _T_4633.imaginary.node @[FFT.scala 75:14]
    stage_outputs_3_0.real.node <= _T_4633.real.node @[FFT.scala 75:14]
    stage_outputs_3_1.imaginary.node <= _T_4699.imaginary.node @[FFT.scala 75:14]
    stage_outputs_3_1.real.node <= _T_4699.real.node @[FFT.scala 75:14]
    cmem _T_4714 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[2] @[FFTUtilities.scala 169:21]
    reg _T_4716 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 15:29]
    when io.in.valid : @[Counter.scala 59:17]
      node _T_4718 = eq(_T_4716, UInt<1>("h01")) @[Counter.scala 23:24]
      node _T_4720 = add(_T_4716, UInt<1>("h01")) @[Counter.scala 24:22]
      node _T_4721 = tail(_T_4720, 1) @[Counter.scala 24:22]
      _T_4716 <= _T_4721 @[Counter.scala 24:13]
      skip @[Counter.scala 59:17]
    node _T_4722 = and(io.in.valid, _T_4718) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_4729 = _T_4714[_T_4716], clock
      _T_4729.imaginary.node <= twiddle[3].imaginary.node @[FFTUtilities.scala 172:29]
      _T_4729.real.node <= twiddle[3].real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_4736 = _T_4714[_T_4716], clock
    inst BBFMultiply_36_1 of BBFMultiply_36 @[DspReal.scala 106:36]
    BBFMultiply_36_1.out is invalid
    BBFMultiply_36_1.in2 is invalid
    BBFMultiply_36_1.in1 is invalid
    BBFMultiply_36_1.in1 <= stage_outputs_2_3.real.node @[DspReal.scala 81:21]
    BBFMultiply_36_1.in2 <= _T_4736.real.node @[DspReal.scala 82:21]
    wire _T_4740 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4740 is invalid @[DspReal.scala 83:19]
    _T_4740.node <= BBFMultiply_36_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_37_1 of BBFMultiply_37 @[DspReal.scala 106:36]
    BBFMultiply_37_1.out is invalid
    BBFMultiply_37_1.in2 is invalid
    BBFMultiply_37_1.in1 is invalid
    BBFMultiply_37_1.in1 <= stage_outputs_2_3.imaginary.node @[DspReal.scala 81:21]
    BBFMultiply_37_1.in2 <= _T_4736.imaginary.node @[DspReal.scala 82:21]
    wire _T_4746 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4746 is invalid @[DspReal.scala 83:19]
    _T_4746.node <= BBFMultiply_37_1.out @[DspReal.scala 84:14]
    wire _T_4752 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_4752 is invalid @[DspReal.scala 165:19]
    _T_4752.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_34_1 of BBFSubtract_34 @[DspReal.scala 102:36]
    BBFSubtract_34_1.out is invalid
    BBFSubtract_34_1.in2 is invalid
    BBFSubtract_34_1.in1 is invalid
    BBFSubtract_34_1.in1 <= _T_4752.node @[DspReal.scala 81:21]
    BBFSubtract_34_1.in2 <= _T_4746.node @[DspReal.scala 82:21]
    wire _T_4759 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4759 is invalid @[DspReal.scala 83:19]
    _T_4759.node <= BBFSubtract_34_1.out @[DspReal.scala 84:14]
    inst BBFAdd_54_1 of BBFAdd_54 @[DspReal.scala 98:36]
    BBFAdd_54_1.out is invalid
    BBFAdd_54_1.in2 is invalid
    BBFAdd_54_1.in1 is invalid
    BBFAdd_54_1.in1 <= _T_4740.node @[DspReal.scala 81:21]
    BBFAdd_54_1.in2 <= _T_4759.node @[DspReal.scala 82:21]
    wire _T_4765 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4765 is invalid @[DspReal.scala 83:19]
    _T_4765.node <= BBFAdd_54_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_38_1 of BBFMultiply_38 @[DspReal.scala 106:36]
    BBFMultiply_38_1.out is invalid
    BBFMultiply_38_1.in2 is invalid
    BBFMultiply_38_1.in1 is invalid
    BBFMultiply_38_1.in1 <= stage_outputs_2_3.real.node @[DspReal.scala 81:21]
    BBFMultiply_38_1.in2 <= _T_4736.imaginary.node @[DspReal.scala 82:21]
    wire _T_4771 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4771 is invalid @[DspReal.scala 83:19]
    _T_4771.node <= BBFMultiply_38_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_39_1 of BBFMultiply_39 @[DspReal.scala 106:36]
    BBFMultiply_39_1.out is invalid
    BBFMultiply_39_1.in2 is invalid
    BBFMultiply_39_1.in1 is invalid
    BBFMultiply_39_1.in1 <= stage_outputs_2_3.imaginary.node @[DspReal.scala 81:21]
    BBFMultiply_39_1.in2 <= _T_4736.real.node @[DspReal.scala 82:21]
    wire _T_4777 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4777 is invalid @[DspReal.scala 83:19]
    _T_4777.node <= BBFMultiply_39_1.out @[DspReal.scala 84:14]
    inst BBFAdd_55_1 of BBFAdd_55 @[DspReal.scala 98:36]
    BBFAdd_55_1.out is invalid
    BBFAdd_55_1.in2 is invalid
    BBFAdd_55_1.in1 is invalid
    BBFAdd_55_1.in1 <= _T_4771.node @[DspReal.scala 81:21]
    BBFAdd_55_1.in2 <= _T_4777.node @[DspReal.scala 82:21]
    wire _T_4783 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4783 is invalid @[DspReal.scala 83:19]
    _T_4783.node <= BBFAdd_55_1.out @[DspReal.scala 84:14]
    wire _T_4799 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_4799 is invalid @[DspComplex.scala 14:22]
    _T_4799.real.node <= _T_4765.node @[DspComplex.scala 15:17]
    _T_4799.imaginary.node <= _T_4783.node @[DspComplex.scala 16:22]
    inst BBFAdd_56_1 of BBFAdd_56 @[DspReal.scala 98:36]
    BBFAdd_56_1.out is invalid
    BBFAdd_56_1.in2 is invalid
    BBFAdd_56_1.in1 is invalid
    BBFAdd_56_1.in1 <= stage_outputs_2_2.real.node @[DspReal.scala 81:21]
    BBFAdd_56_1.in2 <= _T_4799.real.node @[DspReal.scala 82:21]
    wire _T_4803 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4803 is invalid @[DspReal.scala 83:19]
    _T_4803.node <= BBFAdd_56_1.out @[DspReal.scala 84:14]
    inst BBFAdd_57_1 of BBFAdd_57 @[DspReal.scala 98:36]
    BBFAdd_57_1.out is invalid
    BBFAdd_57_1.in2 is invalid
    BBFAdd_57_1.in1 is invalid
    BBFAdd_57_1.in1 <= stage_outputs_2_2.imaginary.node @[DspReal.scala 81:21]
    BBFAdd_57_1.in2 <= _T_4799.imaginary.node @[DspReal.scala 82:21]
    wire _T_4809 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4809 is invalid @[DspReal.scala 83:19]
    _T_4809.node <= BBFAdd_57_1.out @[DspReal.scala 84:14]
    wire _T_4825 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_4825 is invalid @[DspComplex.scala 14:22]
    _T_4825.real.node <= _T_4803.node @[DspComplex.scala 15:17]
    _T_4825.imaginary.node <= _T_4809.node @[DspComplex.scala 16:22]
    wire _T_4829 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_4829 is invalid @[DspReal.scala 165:19]
    _T_4829.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_35_1 of BBFSubtract_35 @[DspReal.scala 102:36]
    BBFSubtract_35_1.out is invalid
    BBFSubtract_35_1.in2 is invalid
    BBFSubtract_35_1.in1 is invalid
    BBFSubtract_35_1.in1 <= _T_4829.node @[DspReal.scala 81:21]
    BBFSubtract_35_1.in2 <= _T_4799.real.node @[DspReal.scala 82:21]
    wire _T_4836 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4836 is invalid @[DspReal.scala 83:19]
    _T_4836.node <= BBFSubtract_35_1.out @[DspReal.scala 84:14]
    wire _T_4842 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_4842 is invalid @[DspReal.scala 165:19]
    _T_4842.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_36_1 of BBFSubtract_36 @[DspReal.scala 102:36]
    BBFSubtract_36_1.out is invalid
    BBFSubtract_36_1.in2 is invalid
    BBFSubtract_36_1.in1 is invalid
    BBFSubtract_36_1.in1 <= _T_4842.node @[DspReal.scala 81:21]
    BBFSubtract_36_1.in2 <= _T_4799.imaginary.node @[DspReal.scala 82:21]
    wire _T_4849 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4849 is invalid @[DspReal.scala 83:19]
    _T_4849.node <= BBFSubtract_36_1.out @[DspReal.scala 84:14]
    wire _T_4865 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_4865 is invalid @[DspComplex.scala 14:22]
    _T_4865.real.node <= _T_4836.node @[DspComplex.scala 15:17]
    _T_4865.imaginary.node <= _T_4849.node @[DspComplex.scala 16:22]
    inst BBFAdd_58_1 of BBFAdd_58 @[DspReal.scala 98:36]
    BBFAdd_58_1.out is invalid
    BBFAdd_58_1.in2 is invalid
    BBFAdd_58_1.in1 is invalid
    BBFAdd_58_1.in1 <= stage_outputs_2_2.real.node @[DspReal.scala 81:21]
    BBFAdd_58_1.in2 <= _T_4865.real.node @[DspReal.scala 82:21]
    wire _T_4869 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4869 is invalid @[DspReal.scala 83:19]
    _T_4869.node <= BBFAdd_58_1.out @[DspReal.scala 84:14]
    inst BBFAdd_59_1 of BBFAdd_59 @[DspReal.scala 98:36]
    BBFAdd_59_1.out is invalid
    BBFAdd_59_1.in2 is invalid
    BBFAdd_59_1.in1 is invalid
    BBFAdd_59_1.in1 <= stage_outputs_2_2.imaginary.node @[DspReal.scala 81:21]
    BBFAdd_59_1.in2 <= _T_4865.imaginary.node @[DspReal.scala 82:21]
    wire _T_4875 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4875 is invalid @[DspReal.scala 83:19]
    _T_4875.node <= BBFAdd_59_1.out @[DspReal.scala 84:14]
    wire _T_4891 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_4891 is invalid @[DspComplex.scala 14:22]
    _T_4891.real.node <= _T_4869.node @[DspComplex.scala 15:17]
    _T_4891.imaginary.node <= _T_4875.node @[DspComplex.scala 16:22]
    stage_outputs_3_2.imaginary.node <= _T_4825.imaginary.node @[FFT.scala 75:14]
    stage_outputs_3_2.real.node <= _T_4825.real.node @[FFT.scala 75:14]
    stage_outputs_3_3.imaginary.node <= _T_4891.imaginary.node @[FFT.scala 75:14]
    stage_outputs_3_3.real.node <= _T_4891.real.node @[FFT.scala 75:14]
    cmem _T_4906 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[2] @[FFTUtilities.scala 169:21]
    reg _T_4908 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 15:29]
    when io.in.valid : @[Counter.scala 59:17]
      node _T_4910 = eq(_T_4908, UInt<1>("h01")) @[Counter.scala 23:24]
      node _T_4912 = add(_T_4908, UInt<1>("h01")) @[Counter.scala 24:22]
      node _T_4913 = tail(_T_4912, 1) @[Counter.scala 24:22]
      _T_4908 <= _T_4913 @[Counter.scala 24:13]
      skip @[Counter.scala 59:17]
    node _T_4914 = and(io.in.valid, _T_4910) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_4921 = _T_4906[_T_4908], clock
      _T_4921.imaginary.node <= twiddle[5].imaginary.node @[FFTUtilities.scala 172:29]
      _T_4921.real.node <= twiddle[5].real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_4928 = _T_4906[_T_4908], clock
    inst BBFMultiply_40_1 of BBFMultiply_40 @[DspReal.scala 106:36]
    BBFMultiply_40_1.out is invalid
    BBFMultiply_40_1.in2 is invalid
    BBFMultiply_40_1.in1 is invalid
    BBFMultiply_40_1.in1 <= stage_outputs_2_5.real.node @[DspReal.scala 81:21]
    BBFMultiply_40_1.in2 <= _T_4928.real.node @[DspReal.scala 82:21]
    wire _T_4932 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4932 is invalid @[DspReal.scala 83:19]
    _T_4932.node <= BBFMultiply_40_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_41_1 of BBFMultiply_41 @[DspReal.scala 106:36]
    BBFMultiply_41_1.out is invalid
    BBFMultiply_41_1.in2 is invalid
    BBFMultiply_41_1.in1 is invalid
    BBFMultiply_41_1.in1 <= stage_outputs_2_5.imaginary.node @[DspReal.scala 81:21]
    BBFMultiply_41_1.in2 <= _T_4928.imaginary.node @[DspReal.scala 82:21]
    wire _T_4938 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4938 is invalid @[DspReal.scala 83:19]
    _T_4938.node <= BBFMultiply_41_1.out @[DspReal.scala 84:14]
    wire _T_4944 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_4944 is invalid @[DspReal.scala 165:19]
    _T_4944.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_37_1 of BBFSubtract_37 @[DspReal.scala 102:36]
    BBFSubtract_37_1.out is invalid
    BBFSubtract_37_1.in2 is invalid
    BBFSubtract_37_1.in1 is invalid
    BBFSubtract_37_1.in1 <= _T_4944.node @[DspReal.scala 81:21]
    BBFSubtract_37_1.in2 <= _T_4938.node @[DspReal.scala 82:21]
    wire _T_4951 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4951 is invalid @[DspReal.scala 83:19]
    _T_4951.node <= BBFSubtract_37_1.out @[DspReal.scala 84:14]
    inst BBFAdd_60_1 of BBFAdd_60 @[DspReal.scala 98:36]
    BBFAdd_60_1.out is invalid
    BBFAdd_60_1.in2 is invalid
    BBFAdd_60_1.in1 is invalid
    BBFAdd_60_1.in1 <= _T_4932.node @[DspReal.scala 81:21]
    BBFAdd_60_1.in2 <= _T_4951.node @[DspReal.scala 82:21]
    wire _T_4957 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4957 is invalid @[DspReal.scala 83:19]
    _T_4957.node <= BBFAdd_60_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_42_1 of BBFMultiply_42 @[DspReal.scala 106:36]
    BBFMultiply_42_1.out is invalid
    BBFMultiply_42_1.in2 is invalid
    BBFMultiply_42_1.in1 is invalid
    BBFMultiply_42_1.in1 <= stage_outputs_2_5.real.node @[DspReal.scala 81:21]
    BBFMultiply_42_1.in2 <= _T_4928.imaginary.node @[DspReal.scala 82:21]
    wire _T_4963 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4963 is invalid @[DspReal.scala 83:19]
    _T_4963.node <= BBFMultiply_42_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_43_1 of BBFMultiply_43 @[DspReal.scala 106:36]
    BBFMultiply_43_1.out is invalid
    BBFMultiply_43_1.in2 is invalid
    BBFMultiply_43_1.in1 is invalid
    BBFMultiply_43_1.in1 <= stage_outputs_2_5.imaginary.node @[DspReal.scala 81:21]
    BBFMultiply_43_1.in2 <= _T_4928.real.node @[DspReal.scala 82:21]
    wire _T_4969 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4969 is invalid @[DspReal.scala 83:19]
    _T_4969.node <= BBFMultiply_43_1.out @[DspReal.scala 84:14]
    inst BBFAdd_61_1 of BBFAdd_61 @[DspReal.scala 98:36]
    BBFAdd_61_1.out is invalid
    BBFAdd_61_1.in2 is invalid
    BBFAdd_61_1.in1 is invalid
    BBFAdd_61_1.in1 <= _T_4963.node @[DspReal.scala 81:21]
    BBFAdd_61_1.in2 <= _T_4969.node @[DspReal.scala 82:21]
    wire _T_4975 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4975 is invalid @[DspReal.scala 83:19]
    _T_4975.node <= BBFAdd_61_1.out @[DspReal.scala 84:14]
    wire _T_4991 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_4991 is invalid @[DspComplex.scala 14:22]
    _T_4991.real.node <= _T_4957.node @[DspComplex.scala 15:17]
    _T_4991.imaginary.node <= _T_4975.node @[DspComplex.scala 16:22]
    inst BBFAdd_62_1 of BBFAdd_62 @[DspReal.scala 98:36]
    BBFAdd_62_1.out is invalid
    BBFAdd_62_1.in2 is invalid
    BBFAdd_62_1.in1 is invalid
    BBFAdd_62_1.in1 <= stage_outputs_2_4.real.node @[DspReal.scala 81:21]
    BBFAdd_62_1.in2 <= _T_4991.real.node @[DspReal.scala 82:21]
    wire _T_4995 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_4995 is invalid @[DspReal.scala 83:19]
    _T_4995.node <= BBFAdd_62_1.out @[DspReal.scala 84:14]
    inst BBFAdd_63_1 of BBFAdd_63 @[DspReal.scala 98:36]
    BBFAdd_63_1.out is invalid
    BBFAdd_63_1.in2 is invalid
    BBFAdd_63_1.in1 is invalid
    BBFAdd_63_1.in1 <= stage_outputs_2_4.imaginary.node @[DspReal.scala 81:21]
    BBFAdd_63_1.in2 <= _T_4991.imaginary.node @[DspReal.scala 82:21]
    wire _T_5001 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_5001 is invalid @[DspReal.scala 83:19]
    _T_5001.node <= BBFAdd_63_1.out @[DspReal.scala 84:14]
    wire _T_5017 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_5017 is invalid @[DspComplex.scala 14:22]
    _T_5017.real.node <= _T_4995.node @[DspComplex.scala 15:17]
    _T_5017.imaginary.node <= _T_5001.node @[DspComplex.scala 16:22]
    wire _T_5021 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_5021 is invalid @[DspReal.scala 165:19]
    _T_5021.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_38_1 of BBFSubtract_38 @[DspReal.scala 102:36]
    BBFSubtract_38_1.out is invalid
    BBFSubtract_38_1.in2 is invalid
    BBFSubtract_38_1.in1 is invalid
    BBFSubtract_38_1.in1 <= _T_5021.node @[DspReal.scala 81:21]
    BBFSubtract_38_1.in2 <= _T_4991.real.node @[DspReal.scala 82:21]
    wire _T_5028 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_5028 is invalid @[DspReal.scala 83:19]
    _T_5028.node <= BBFSubtract_38_1.out @[DspReal.scala 84:14]
    wire _T_5034 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_5034 is invalid @[DspReal.scala 165:19]
    _T_5034.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_39_1 of BBFSubtract_39 @[DspReal.scala 102:36]
    BBFSubtract_39_1.out is invalid
    BBFSubtract_39_1.in2 is invalid
    BBFSubtract_39_1.in1 is invalid
    BBFSubtract_39_1.in1 <= _T_5034.node @[DspReal.scala 81:21]
    BBFSubtract_39_1.in2 <= _T_4991.imaginary.node @[DspReal.scala 82:21]
    wire _T_5041 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_5041 is invalid @[DspReal.scala 83:19]
    _T_5041.node <= BBFSubtract_39_1.out @[DspReal.scala 84:14]
    wire _T_5057 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_5057 is invalid @[DspComplex.scala 14:22]
    _T_5057.real.node <= _T_5028.node @[DspComplex.scala 15:17]
    _T_5057.imaginary.node <= _T_5041.node @[DspComplex.scala 16:22]
    inst BBFAdd_64_1 of BBFAdd_64 @[DspReal.scala 98:36]
    BBFAdd_64_1.out is invalid
    BBFAdd_64_1.in2 is invalid
    BBFAdd_64_1.in1 is invalid
    BBFAdd_64_1.in1 <= stage_outputs_2_4.real.node @[DspReal.scala 81:21]
    BBFAdd_64_1.in2 <= _T_5057.real.node @[DspReal.scala 82:21]
    wire _T_5061 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_5061 is invalid @[DspReal.scala 83:19]
    _T_5061.node <= BBFAdd_64_1.out @[DspReal.scala 84:14]
    inst BBFAdd_65_1 of BBFAdd_65 @[DspReal.scala 98:36]
    BBFAdd_65_1.out is invalid
    BBFAdd_65_1.in2 is invalid
    BBFAdd_65_1.in1 is invalid
    BBFAdd_65_1.in1 <= stage_outputs_2_4.imaginary.node @[DspReal.scala 81:21]
    BBFAdd_65_1.in2 <= _T_5057.imaginary.node @[DspReal.scala 82:21]
    wire _T_5067 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_5067 is invalid @[DspReal.scala 83:19]
    _T_5067.node <= BBFAdd_65_1.out @[DspReal.scala 84:14]
    wire _T_5083 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_5083 is invalid @[DspComplex.scala 14:22]
    _T_5083.real.node <= _T_5061.node @[DspComplex.scala 15:17]
    _T_5083.imaginary.node <= _T_5067.node @[DspComplex.scala 16:22]
    stage_outputs_3_4.imaginary.node <= _T_5017.imaginary.node @[FFT.scala 75:14]
    stage_outputs_3_4.real.node <= _T_5017.real.node @[FFT.scala 75:14]
    stage_outputs_3_5.imaginary.node <= _T_5083.imaginary.node @[FFT.scala 75:14]
    stage_outputs_3_5.real.node <= _T_5083.real.node @[FFT.scala 75:14]
    cmem _T_5098 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[2] @[FFTUtilities.scala 169:21]
    reg _T_5100 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 15:29]
    when io.in.valid : @[Counter.scala 59:17]
      node _T_5102 = eq(_T_5100, UInt<1>("h01")) @[Counter.scala 23:24]
      node _T_5104 = add(_T_5100, UInt<1>("h01")) @[Counter.scala 24:22]
      node _T_5105 = tail(_T_5104, 1) @[Counter.scala 24:22]
      _T_5100 <= _T_5105 @[Counter.scala 24:13]
      skip @[Counter.scala 59:17]
    node _T_5106 = and(io.in.valid, _T_5102) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_5113 = _T_5098[_T_5100], clock
      _T_5113.imaginary.node <= twiddle[6].imaginary.node @[FFTUtilities.scala 172:29]
      _T_5113.real.node <= twiddle[6].real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_5120 = _T_5098[_T_5100], clock
    inst BBFMultiply_44_1 of BBFMultiply_44 @[DspReal.scala 106:36]
    BBFMultiply_44_1.out is invalid
    BBFMultiply_44_1.in2 is invalid
    BBFMultiply_44_1.in1 is invalid
    BBFMultiply_44_1.in1 <= stage_outputs_2_7.real.node @[DspReal.scala 81:21]
    BBFMultiply_44_1.in2 <= _T_5120.real.node @[DspReal.scala 82:21]
    wire _T_5124 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_5124 is invalid @[DspReal.scala 83:19]
    _T_5124.node <= BBFMultiply_44_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_45_1 of BBFMultiply_45 @[DspReal.scala 106:36]
    BBFMultiply_45_1.out is invalid
    BBFMultiply_45_1.in2 is invalid
    BBFMultiply_45_1.in1 is invalid
    BBFMultiply_45_1.in1 <= stage_outputs_2_7.imaginary.node @[DspReal.scala 81:21]
    BBFMultiply_45_1.in2 <= _T_5120.imaginary.node @[DspReal.scala 82:21]
    wire _T_5130 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_5130 is invalid @[DspReal.scala 83:19]
    _T_5130.node <= BBFMultiply_45_1.out @[DspReal.scala 84:14]
    wire _T_5136 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_5136 is invalid @[DspReal.scala 165:19]
    _T_5136.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_40_1 of BBFSubtract_40 @[DspReal.scala 102:36]
    BBFSubtract_40_1.out is invalid
    BBFSubtract_40_1.in2 is invalid
    BBFSubtract_40_1.in1 is invalid
    BBFSubtract_40_1.in1 <= _T_5136.node @[DspReal.scala 81:21]
    BBFSubtract_40_1.in2 <= _T_5130.node @[DspReal.scala 82:21]
    wire _T_5143 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_5143 is invalid @[DspReal.scala 83:19]
    _T_5143.node <= BBFSubtract_40_1.out @[DspReal.scala 84:14]
    inst BBFAdd_66_1 of BBFAdd_66 @[DspReal.scala 98:36]
    BBFAdd_66_1.out is invalid
    BBFAdd_66_1.in2 is invalid
    BBFAdd_66_1.in1 is invalid
    BBFAdd_66_1.in1 <= _T_5124.node @[DspReal.scala 81:21]
    BBFAdd_66_1.in2 <= _T_5143.node @[DspReal.scala 82:21]
    wire _T_5149 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_5149 is invalid @[DspReal.scala 83:19]
    _T_5149.node <= BBFAdd_66_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_46_1 of BBFMultiply_46 @[DspReal.scala 106:36]
    BBFMultiply_46_1.out is invalid
    BBFMultiply_46_1.in2 is invalid
    BBFMultiply_46_1.in1 is invalid
    BBFMultiply_46_1.in1 <= stage_outputs_2_7.real.node @[DspReal.scala 81:21]
    BBFMultiply_46_1.in2 <= _T_5120.imaginary.node @[DspReal.scala 82:21]
    wire _T_5155 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_5155 is invalid @[DspReal.scala 83:19]
    _T_5155.node <= BBFMultiply_46_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_47_1 of BBFMultiply_47 @[DspReal.scala 106:36]
    BBFMultiply_47_1.out is invalid
    BBFMultiply_47_1.in2 is invalid
    BBFMultiply_47_1.in1 is invalid
    BBFMultiply_47_1.in1 <= stage_outputs_2_7.imaginary.node @[DspReal.scala 81:21]
    BBFMultiply_47_1.in2 <= _T_5120.real.node @[DspReal.scala 82:21]
    wire _T_5161 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_5161 is invalid @[DspReal.scala 83:19]
    _T_5161.node <= BBFMultiply_47_1.out @[DspReal.scala 84:14]
    inst BBFAdd_67_1 of BBFAdd_67 @[DspReal.scala 98:36]
    BBFAdd_67_1.out is invalid
    BBFAdd_67_1.in2 is invalid
    BBFAdd_67_1.in1 is invalid
    BBFAdd_67_1.in1 <= _T_5155.node @[DspReal.scala 81:21]
    BBFAdd_67_1.in2 <= _T_5161.node @[DspReal.scala 82:21]
    wire _T_5167 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_5167 is invalid @[DspReal.scala 83:19]
    _T_5167.node <= BBFAdd_67_1.out @[DspReal.scala 84:14]
    wire _T_5183 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_5183 is invalid @[DspComplex.scala 14:22]
    _T_5183.real.node <= _T_5149.node @[DspComplex.scala 15:17]
    _T_5183.imaginary.node <= _T_5167.node @[DspComplex.scala 16:22]
    inst BBFAdd_68_1 of BBFAdd_68 @[DspReal.scala 98:36]
    BBFAdd_68_1.out is invalid
    BBFAdd_68_1.in2 is invalid
    BBFAdd_68_1.in1 is invalid
    BBFAdd_68_1.in1 <= stage_outputs_2_6.real.node @[DspReal.scala 81:21]
    BBFAdd_68_1.in2 <= _T_5183.real.node @[DspReal.scala 82:21]
    wire _T_5187 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_5187 is invalid @[DspReal.scala 83:19]
    _T_5187.node <= BBFAdd_68_1.out @[DspReal.scala 84:14]
    inst BBFAdd_69_1 of BBFAdd_69 @[DspReal.scala 98:36]
    BBFAdd_69_1.out is invalid
    BBFAdd_69_1.in2 is invalid
    BBFAdd_69_1.in1 is invalid
    BBFAdd_69_1.in1 <= stage_outputs_2_6.imaginary.node @[DspReal.scala 81:21]
    BBFAdd_69_1.in2 <= _T_5183.imaginary.node @[DspReal.scala 82:21]
    wire _T_5193 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_5193 is invalid @[DspReal.scala 83:19]
    _T_5193.node <= BBFAdd_69_1.out @[DspReal.scala 84:14]
    wire _T_5209 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_5209 is invalid @[DspComplex.scala 14:22]
    _T_5209.real.node <= _T_5187.node @[DspComplex.scala 15:17]
    _T_5209.imaginary.node <= _T_5193.node @[DspComplex.scala 16:22]
    wire _T_5213 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_5213 is invalid @[DspReal.scala 165:19]
    _T_5213.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_41_1 of BBFSubtract_41 @[DspReal.scala 102:36]
    BBFSubtract_41_1.out is invalid
    BBFSubtract_41_1.in2 is invalid
    BBFSubtract_41_1.in1 is invalid
    BBFSubtract_41_1.in1 <= _T_5213.node @[DspReal.scala 81:21]
    BBFSubtract_41_1.in2 <= _T_5183.real.node @[DspReal.scala 82:21]
    wire _T_5220 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_5220 is invalid @[DspReal.scala 83:19]
    _T_5220.node <= BBFSubtract_41_1.out @[DspReal.scala 84:14]
    wire _T_5226 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_5226 is invalid @[DspReal.scala 165:19]
    _T_5226.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_42_1 of BBFSubtract_42 @[DspReal.scala 102:36]
    BBFSubtract_42_1.out is invalid
    BBFSubtract_42_1.in2 is invalid
    BBFSubtract_42_1.in1 is invalid
    BBFSubtract_42_1.in1 <= _T_5226.node @[DspReal.scala 81:21]
    BBFSubtract_42_1.in2 <= _T_5183.imaginary.node @[DspReal.scala 82:21]
    wire _T_5233 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_5233 is invalid @[DspReal.scala 83:19]
    _T_5233.node <= BBFSubtract_42_1.out @[DspReal.scala 84:14]
    wire _T_5249 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_5249 is invalid @[DspComplex.scala 14:22]
    _T_5249.real.node <= _T_5220.node @[DspComplex.scala 15:17]
    _T_5249.imaginary.node <= _T_5233.node @[DspComplex.scala 16:22]
    inst BBFAdd_70_1 of BBFAdd_70 @[DspReal.scala 98:36]
    BBFAdd_70_1.out is invalid
    BBFAdd_70_1.in2 is invalid
    BBFAdd_70_1.in1 is invalid
    BBFAdd_70_1.in1 <= stage_outputs_2_6.real.node @[DspReal.scala 81:21]
    BBFAdd_70_1.in2 <= _T_5249.real.node @[DspReal.scala 82:21]
    wire _T_5253 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_5253 is invalid @[DspReal.scala 83:19]
    _T_5253.node <= BBFAdd_70_1.out @[DspReal.scala 84:14]
    inst BBFAdd_71_1 of BBFAdd_71 @[DspReal.scala 98:36]
    BBFAdd_71_1.out is invalid
    BBFAdd_71_1.in2 is invalid
    BBFAdd_71_1.in1 is invalid
    BBFAdd_71_1.in1 <= stage_outputs_2_6.imaginary.node @[DspReal.scala 81:21]
    BBFAdd_71_1.in2 <= _T_5249.imaginary.node @[DspReal.scala 82:21]
    wire _T_5259 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_5259 is invalid @[DspReal.scala 83:19]
    _T_5259.node <= BBFAdd_71_1.out @[DspReal.scala 84:14]
    wire _T_5275 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_5275 is invalid @[DspComplex.scala 14:22]
    _T_5275.real.node <= _T_5253.node @[DspComplex.scala 15:17]
    _T_5275.imaginary.node <= _T_5259.node @[DspComplex.scala 16:22]
    stage_outputs_3_6.imaginary.node <= _T_5209.imaginary.node @[FFT.scala 75:14]
    stage_outputs_3_6.real.node <= _T_5209.real.node @[FFT.scala 75:14]
    stage_outputs_3_7.imaginary.node <= _T_5275.imaginary.node @[FFT.scala 75:14]
    stage_outputs_3_7.real.node <= _T_5275.real.node @[FFT.scala 75:14]
    io.out.bits[0].imaginary.node <= stage_outputs_3_0.imaginary.node @[FFT.scala 82:15]
    io.out.bits[0].real.node <= stage_outputs_3_0.real.node @[FFT.scala 82:15]
    io.out.bits[1].imaginary.node <= stage_outputs_3_1.imaginary.node @[FFT.scala 82:15]
    io.out.bits[1].real.node <= stage_outputs_3_1.real.node @[FFT.scala 82:15]
    io.out.bits[2].imaginary.node <= stage_outputs_3_2.imaginary.node @[FFT.scala 82:15]
    io.out.bits[2].real.node <= stage_outputs_3_2.real.node @[FFT.scala 82:15]
    io.out.bits[3].imaginary.node <= stage_outputs_3_3.imaginary.node @[FFT.scala 82:15]
    io.out.bits[3].real.node <= stage_outputs_3_3.real.node @[FFT.scala 82:15]
    io.out.bits[4].imaginary.node <= stage_outputs_3_4.imaginary.node @[FFT.scala 82:15]
    io.out.bits[4].real.node <= stage_outputs_3_4.real.node @[FFT.scala 82:15]
    io.out.bits[5].imaginary.node <= stage_outputs_3_5.imaginary.node @[FFT.scala 82:15]
    io.out.bits[5].real.node <= stage_outputs_3_5.real.node @[FFT.scala 82:15]
    io.out.bits[6].imaginary.node <= stage_outputs_3_6.imaginary.node @[FFT.scala 82:15]
    io.out.bits[6].real.node <= stage_outputs_3_6.real.node @[FFT.scala 82:15]
    io.out.bits[7].imaginary.node <= stage_outputs_3_7.imaginary.node @[FFT.scala 82:15]
    io.out.bits[7].real.node <= stage_outputs_3_7.real.node @[FFT.scala 82:15]
    
  extmodule BBFMultiply_48 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFMultiply_49 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFSubtract_43 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFAdd_72 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFMultiply_50 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFMultiply_51 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFAdd_73 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_74 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_75 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFSubtract_44 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFSubtract_45 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFAdd_76 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_77 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFMultiply_52 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFMultiply_53 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFSubtract_46 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFAdd_78 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFMultiply_54 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFMultiply_55 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFAdd_79 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_80 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_81 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFSubtract_47 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFSubtract_48 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFAdd_82 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_83 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFMultiply_56 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFMultiply_57 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFSubtract_49 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFAdd_84 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFMultiply_58 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFMultiply_59 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFAdd_85 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_86 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_87 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFSubtract_50 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFSubtract_51 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFAdd_88 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_89 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFMultiply_60 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFMultiply_61 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFSubtract_52 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFAdd_90 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFMultiply_62 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFMultiply_63 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFMultiply
    
    
  extmodule BBFAdd_91 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_92 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_93 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFSubtract_53 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFSubtract_54 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFSubtract
    
    
  extmodule BBFAdd_94 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  extmodule BBFAdd_95 : 
    output out : UInt<64>
    input in2 : UInt<64>
    input in1 : UInt<64>
    
    defname = BBFAdd
    
    
  module BiplexFFT : 
    input clock : Clock
    input reset : UInt<1>
    output io : {flip in : {valid : UInt<1>, bits : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[8], sync : UInt<1>}, out : {valid : UInt<1>, bits : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[8], sync : UInt<1>}}
    
    io is invalid
    io is invalid
    wire _T_5 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_5 is invalid @[DspReal.scala 165:19]
    _T_5.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_12 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_12 is invalid @[DspReal.scala 165:19]
    _T_12.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_316 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_316 is invalid @[DspReal.scala 165:19]
    _T_316.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_323 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_323 is invalid @[DspReal.scala 165:19]
    _T_323.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire sync_0 : UInt<1> @[FFT.scala 95:49]
    sync_0 is invalid @[FFT.scala 95:49]
    wire sync_1 : UInt<1> @[FFT.scala 95:49]
    sync_1 is invalid @[FFT.scala 95:49]
    node _T_626 = and(io.in.sync, io.in.valid) @[FFT.scala 96:66]
    reg _T_628 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Counter.scala 15:29]
    when io.in.valid : @[Counter.scala 59:17]
      node _T_630 = eq(_T_628, UInt<1>("h01")) @[Counter.scala 23:24]
      node _T_632 = add(_T_628, UInt<1>("h01")) @[Counter.scala 24:22]
      node _T_633 = tail(_T_632, 1) @[Counter.scala 24:22]
      _T_628 <= _T_633 @[Counter.scala 24:13]
      skip @[Counter.scala 59:17]
    node _T_634 = and(io.in.valid, _T_630) @[Counter.scala 60:20]
    when _T_626 : @[CounterWithReset.scala 11:31]
      _T_628 <= UInt<1>("h00") @[CounterWithReset.scala 11:38]
      skip @[CounterWithReset.scala 11:31]
    sync_0 <= _T_628 @[FFT.scala 96:11]
    cmem _T_638 : UInt<1>[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_641 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_643 = _T_638[UInt<1>("h00")], clock
      _T_643 <= sync_0 @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_645 = _T_638[UInt<1>("h00")], clock
    sync_1 <= _T_645 @[FFT.scala 97:89]
    node _T_647 = eq(sync_1, UInt<1>("h00")) @[FFT.scala 98:42]
    io.out.sync <= _T_647 @[FFT.scala 98:15]
    io.out.valid <= io.in.valid @[FFT.scala 99:16]
    wire _T_651 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_651 is invalid @[DspReal.scala 165:19]
    _T_651.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_658 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_658 is invalid @[DspReal.scala 165:19]
    _T_658.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire twiddle_rom : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[4] @[FFT.scala 104:25]
    twiddle_rom is invalid @[FFT.scala 104:25]
    wire _T_735 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_735 is invalid @[DspReal.scala 165:19]
    _T_735.node <= UInt<64>("h03ff0000000000000") @[DspReal.scala 166:14]
    wire _T_742 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_742 is invalid @[DspReal.scala 165:19]
    _T_742.node <= UInt<64>("h08000000000000000") @[DspReal.scala 166:14]
    wire _T_759 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_759 is invalid @[DspComplex.scala 14:22]
    _T_759.real.node <= _T_735.node @[DspComplex.scala 15:17]
    _T_759.imaginary.node <= _T_742.node @[DspComplex.scala 16:22]
    twiddle_rom[0].imaginary.node <= _T_759.imaginary.node @[FFT.scala 105:69]
    twiddle_rom[0].real.node <= _T_759.real.node @[FFT.scala 105:69]
    wire _T_763 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_763 is invalid @[DspReal.scala 165:19]
    _T_763.node <= UInt<64>("h03fed906bcf328d46") @[DspReal.scala 166:14]
    wire _T_770 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_770 is invalid @[DspReal.scala 165:19]
    _T_770.node <= UInt<64>("h0bfd87de2a6aea963") @[DspReal.scala 166:14]
    wire _T_787 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_787 is invalid @[DspComplex.scala 14:22]
    _T_787.real.node <= _T_763.node @[DspComplex.scala 15:17]
    _T_787.imaginary.node <= _T_770.node @[DspComplex.scala 16:22]
    twiddle_rom[1].imaginary.node <= _T_787.imaginary.node @[FFT.scala 105:69]
    twiddle_rom[1].real.node <= _T_787.real.node @[FFT.scala 105:69]
    wire _T_791 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_791 is invalid @[DspReal.scala 165:19]
    _T_791.node <= UInt<64>("h03fe6a09e667f3bcd") @[DspReal.scala 166:14]
    wire _T_798 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_798 is invalid @[DspReal.scala 165:19]
    _T_798.node <= UInt<64>("h0bfe6a09e667f3bcc") @[DspReal.scala 166:14]
    wire _T_815 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_815 is invalid @[DspComplex.scala 14:22]
    _T_815.real.node <= _T_791.node @[DspComplex.scala 15:17]
    _T_815.imaginary.node <= _T_798.node @[DspComplex.scala 16:22]
    twiddle_rom[2].imaginary.node <= _T_815.imaginary.node @[FFT.scala 105:69]
    twiddle_rom[2].real.node <= _T_815.real.node @[FFT.scala 105:69]
    wire _T_819 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_819 is invalid @[DspReal.scala 165:19]
    _T_819.node <= UInt<64>("h03fd87de2a6aea964") @[DspReal.scala 166:14]
    wire _T_826 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_826 is invalid @[DspReal.scala 165:19]
    _T_826.node <= UInt<64>("h0bfed906bcf328d46") @[DspReal.scala 166:14]
    wire _T_843 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_843 is invalid @[DspComplex.scala 14:22]
    _T_843.real.node <= _T_819.node @[DspComplex.scala 15:17]
    _T_843.imaginary.node <= _T_826.node @[DspComplex.scala 16:22]
    twiddle_rom[3].imaginary.node <= _T_843.imaginary.node @[FFT.scala 105:69]
    twiddle_rom[3].real.node <= _T_843.real.node @[FFT.scala 105:69]
    wire indices_rom : UInt<1>[1] @[FFT.scala 106:24]
    indices_rom is invalid @[FFT.scala 106:24]
    indices_rom[0] <= UInt<1>("h00") @[FFT.scala 106:24]
    node _T_854 = add(UInt<1>("h00"), UInt<1>("h00")) @[FFT.scala 107:91]
    wire _T_860 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_860 is invalid @[DspReal.scala 165:19]
    _T_860.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_867 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_867 is invalid @[DspReal.scala 165:19]
    _T_867.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_884 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 108:49]
    _T_884 is invalid @[FFT.scala 108:49]
    wire twiddle : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFT.scala 108:44]
    twiddle is invalid @[FFT.scala 108:44]
    twiddle[0].imaginary.node <= _T_884.imaginary.node @[FFT.scala 108:44]
    twiddle[0].real.node <= _T_884.real.node @[FFT.scala 108:44]
    wire _T_974 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFT.scala 113:19]
    _T_974 is invalid @[FFT.scala 113:19]
    _T_974[0].imaginary.node <= twiddle_rom[indices_rom[UInt<1>("h00")]].imaginary.node @[FFT.scala 113:19]
    _T_974[0].real.node <= twiddle_rom[indices_rom[UInt<1>("h00")]].real.node @[FFT.scala 113:19]
    twiddle[0].imaginary.node <= _T_974[0].imaginary.node @[FFT.scala 113:13]
    twiddle[0].real.node <= _T_974[0].real.node @[FFT.scala 113:13]
    wire _T_1005 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1005 is invalid @[DspReal.scala 165:19]
    _T_1005.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1012 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1012 is invalid @[DspReal.scala 165:19]
    _T_1012.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_0_0 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 120:78]
    stage_outputs_0_0 is invalid @[FFT.scala 120:78]
    wire _T_1032 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1032 is invalid @[DspReal.scala 165:19]
    _T_1032.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1039 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1039 is invalid @[DspReal.scala 165:19]
    _T_1039.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_0_1 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 120:78]
    stage_outputs_0_1 is invalid @[FFT.scala 120:78]
    wire _T_1059 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1059 is invalid @[DspReal.scala 165:19]
    _T_1059.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1066 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1066 is invalid @[DspReal.scala 165:19]
    _T_1066.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_0_2 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 120:78]
    stage_outputs_0_2 is invalid @[FFT.scala 120:78]
    wire _T_1086 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1086 is invalid @[DspReal.scala 165:19]
    _T_1086.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1093 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1093 is invalid @[DspReal.scala 165:19]
    _T_1093.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_0_3 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 120:78]
    stage_outputs_0_3 is invalid @[FFT.scala 120:78]
    wire _T_1113 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1113 is invalid @[DspReal.scala 165:19]
    _T_1113.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1120 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1120 is invalid @[DspReal.scala 165:19]
    _T_1120.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_0_4 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 120:78]
    stage_outputs_0_4 is invalid @[FFT.scala 120:78]
    wire _T_1140 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1140 is invalid @[DspReal.scala 165:19]
    _T_1140.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1147 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1147 is invalid @[DspReal.scala 165:19]
    _T_1147.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_0_5 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 120:78]
    stage_outputs_0_5 is invalid @[FFT.scala 120:78]
    wire _T_1167 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1167 is invalid @[DspReal.scala 165:19]
    _T_1167.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1174 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1174 is invalid @[DspReal.scala 165:19]
    _T_1174.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_0_6 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 120:78]
    stage_outputs_0_6 is invalid @[FFT.scala 120:78]
    wire _T_1194 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1194 is invalid @[DspReal.scala 165:19]
    _T_1194.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1201 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1201 is invalid @[DspReal.scala 165:19]
    _T_1201.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_0_7 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 120:78]
    stage_outputs_0_7 is invalid @[FFT.scala 120:78]
    wire _T_1221 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1221 is invalid @[DspReal.scala 165:19]
    _T_1221.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1228 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1228 is invalid @[DspReal.scala 165:19]
    _T_1228.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_1_0 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 120:78]
    stage_outputs_1_0 is invalid @[FFT.scala 120:78]
    wire _T_1248 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1248 is invalid @[DspReal.scala 165:19]
    _T_1248.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1255 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1255 is invalid @[DspReal.scala 165:19]
    _T_1255.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_1_1 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 120:78]
    stage_outputs_1_1 is invalid @[FFT.scala 120:78]
    wire _T_1275 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1275 is invalid @[DspReal.scala 165:19]
    _T_1275.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1282 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1282 is invalid @[DspReal.scala 165:19]
    _T_1282.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_1_2 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 120:78]
    stage_outputs_1_2 is invalid @[FFT.scala 120:78]
    wire _T_1302 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1302 is invalid @[DspReal.scala 165:19]
    _T_1302.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1309 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1309 is invalid @[DspReal.scala 165:19]
    _T_1309.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_1_3 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 120:78]
    stage_outputs_1_3 is invalid @[FFT.scala 120:78]
    wire _T_1329 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1329 is invalid @[DspReal.scala 165:19]
    _T_1329.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1336 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1336 is invalid @[DspReal.scala 165:19]
    _T_1336.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_1_4 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 120:78]
    stage_outputs_1_4 is invalid @[FFT.scala 120:78]
    wire _T_1356 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1356 is invalid @[DspReal.scala 165:19]
    _T_1356.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1363 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1363 is invalid @[DspReal.scala 165:19]
    _T_1363.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_1_5 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 120:78]
    stage_outputs_1_5 is invalid @[FFT.scala 120:78]
    wire _T_1383 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1383 is invalid @[DspReal.scala 165:19]
    _T_1383.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1390 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1390 is invalid @[DspReal.scala 165:19]
    _T_1390.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_1_6 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 120:78]
    stage_outputs_1_6 is invalid @[FFT.scala 120:78]
    wire _T_1410 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1410 is invalid @[DspReal.scala 165:19]
    _T_1410.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1417 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1417 is invalid @[DspReal.scala 165:19]
    _T_1417.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_1_7 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 120:78]
    stage_outputs_1_7 is invalid @[FFT.scala 120:78]
    wire _T_1437 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1437 is invalid @[DspReal.scala 165:19]
    _T_1437.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1444 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1444 is invalid @[DspReal.scala 165:19]
    _T_1444.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_2_0 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 120:78]
    stage_outputs_2_0 is invalid @[FFT.scala 120:78]
    wire _T_1464 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1464 is invalid @[DspReal.scala 165:19]
    _T_1464.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1471 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1471 is invalid @[DspReal.scala 165:19]
    _T_1471.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_2_1 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 120:78]
    stage_outputs_2_1 is invalid @[FFT.scala 120:78]
    wire _T_1491 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1491 is invalid @[DspReal.scala 165:19]
    _T_1491.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1498 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1498 is invalid @[DspReal.scala 165:19]
    _T_1498.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_2_2 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 120:78]
    stage_outputs_2_2 is invalid @[FFT.scala 120:78]
    wire _T_1518 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1518 is invalid @[DspReal.scala 165:19]
    _T_1518.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1525 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1525 is invalid @[DspReal.scala 165:19]
    _T_1525.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_2_3 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 120:78]
    stage_outputs_2_3 is invalid @[FFT.scala 120:78]
    wire _T_1545 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1545 is invalid @[DspReal.scala 165:19]
    _T_1545.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1552 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1552 is invalid @[DspReal.scala 165:19]
    _T_1552.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_2_4 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 120:78]
    stage_outputs_2_4 is invalid @[FFT.scala 120:78]
    wire _T_1572 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1572 is invalid @[DspReal.scala 165:19]
    _T_1572.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1579 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1579 is invalid @[DspReal.scala 165:19]
    _T_1579.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_2_5 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 120:78]
    stage_outputs_2_5 is invalid @[FFT.scala 120:78]
    wire _T_1599 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1599 is invalid @[DspReal.scala 165:19]
    _T_1599.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1606 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1606 is invalid @[DspReal.scala 165:19]
    _T_1606.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_2_6 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 120:78]
    stage_outputs_2_6 is invalid @[FFT.scala 120:78]
    wire _T_1626 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1626 is invalid @[DspReal.scala 165:19]
    _T_1626.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_1633 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1633 is invalid @[DspReal.scala 165:19]
    _T_1633.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire stage_outputs_2_7 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[FFT.scala 120:78]
    stage_outputs_2_7 is invalid @[FFT.scala 120:78]
    stage_outputs_0_0.imaginary.node <= io.in.bits[0].imaginary.node @[FFT.scala 121:67]
    stage_outputs_0_0.real.node <= io.in.bits[0].real.node @[FFT.scala 121:67]
    stage_outputs_0_1.imaginary.node <= io.in.bits[1].imaginary.node @[FFT.scala 121:67]
    stage_outputs_0_1.real.node <= io.in.bits[1].real.node @[FFT.scala 121:67]
    stage_outputs_0_2.imaginary.node <= io.in.bits[2].imaginary.node @[FFT.scala 121:67]
    stage_outputs_0_2.real.node <= io.in.bits[2].real.node @[FFT.scala 121:67]
    stage_outputs_0_3.imaginary.node <= io.in.bits[3].imaginary.node @[FFT.scala 121:67]
    stage_outputs_0_3.real.node <= io.in.bits[3].real.node @[FFT.scala 121:67]
    stage_outputs_0_4.imaginary.node <= io.in.bits[4].imaginary.node @[FFT.scala 121:67]
    stage_outputs_0_4.real.node <= io.in.bits[4].real.node @[FFT.scala 121:67]
    stage_outputs_0_5.imaginary.node <= io.in.bits[5].imaginary.node @[FFT.scala 121:67]
    stage_outputs_0_5.real.node <= io.in.bits[5].real.node @[FFT.scala 121:67]
    stage_outputs_0_6.imaginary.node <= io.in.bits[6].imaginary.node @[FFT.scala 121:67]
    stage_outputs_0_6.real.node <= io.in.bits[6].real.node @[FFT.scala 121:67]
    stage_outputs_0_7.imaginary.node <= io.in.bits[7].imaginary.node @[FFT.scala 121:67]
    stage_outputs_0_7.real.node <= io.in.bits[7].real.node @[FFT.scala 121:67]
    cmem _T_1664 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_1667 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_1675 = _T_1664[UInt<1>("h00")], clock
      _T_1675.imaginary.node <= stage_outputs_0_1.imaginary.node @[FFTUtilities.scala 172:29]
      _T_1675.real.node <= stage_outputs_0_1.real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_1683 = _T_1664[UInt<1>("h00")], clock
    wire _T_1725 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[2] @[FFT.scala 132:38]
    _T_1725 is invalid @[FFT.scala 132:38]
    _T_1725[0].imaginary.node <= stage_outputs_0_0.imaginary.node @[FFT.scala 132:38]
    _T_1725[0].real.node <= stage_outputs_0_0.real.node @[FFT.scala 132:38]
    _T_1725[1].imaginary.node <= _T_1683.imaginary.node @[FFT.scala 132:38]
    _T_1725[1].real.node <= _T_1683.real.node @[FFT.scala 132:38]
    node _T_1766 = bits(sync_0, 0, 0) @[FFT.scala 132:167]
    wire _T_1768 : UInt<1> @[FFTUtilities.scala 88:21]
    _T_1768 is invalid @[FFTUtilities.scala 88:21]
    node _T_1770 = add(_T_1766, UInt<1>("h00")) @[FFTUtilities.scala 89:20]
    node _T_1771 = tail(_T_1770, 1) @[FFTUtilities.scala 89:20]
    _T_1768 <= _T_1771 @[FFTUtilities.scala 89:11]
    wire _T_1786 : UInt<1> @[FFTUtilities.scala 88:21]
    _T_1786 is invalid @[FFTUtilities.scala 88:21]
    node _T_1788 = add(_T_1766, UInt<1>("h01")) @[FFTUtilities.scala 89:20]
    node _T_1789 = tail(_T_1788, 1) @[FFTUtilities.scala 89:20]
    _T_1786 <= _T_1789 @[FFTUtilities.scala 89:11]
    wire _T_1844 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[2] @[FFTUtilities.scala 87:8]
    _T_1844 is invalid @[FFTUtilities.scala 87:8]
    _T_1844[0].imaginary.node <= _T_1725[_T_1768].imaginary.node @[FFTUtilities.scala 87:8]
    _T_1844[0].real.node <= _T_1725[_T_1768].real.node @[FFTUtilities.scala 87:8]
    _T_1844[1].imaginary.node <= _T_1725[_T_1786].imaginary.node @[FFTUtilities.scala 87:8]
    _T_1844[1].real.node <= _T_1725[_T_1786].real.node @[FFTUtilities.scala 87:8]
    cmem _T_1899 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_1902 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_1910 = _T_1899[UInt<1>("h00")], clock
      _T_1910.imaginary.node <= _T_1844[0].imaginary.node @[FFTUtilities.scala 172:29]
      _T_1910.real.node <= _T_1844[0].real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_1918 = _T_1899[UInt<1>("h00")], clock
    inst BBFMultiply_48_1 of BBFMultiply_48 @[DspReal.scala 106:36]
    BBFMultiply_48_1.out is invalid
    BBFMultiply_48_1.in2 is invalid
    BBFMultiply_48_1.in1 is invalid
    BBFMultiply_48_1.in1 <= _T_1844[1].real.node @[DspReal.scala 81:21]
    BBFMultiply_48_1.in2 <= twiddle[0].real.node @[DspReal.scala 82:21]
    wire _T_1922 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_1922 is invalid @[DspReal.scala 83:19]
    _T_1922.node <= BBFMultiply_48_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_49_1 of BBFMultiply_49 @[DspReal.scala 106:36]
    BBFMultiply_49_1.out is invalid
    BBFMultiply_49_1.in2 is invalid
    BBFMultiply_49_1.in1 is invalid
    BBFMultiply_49_1.in1 <= _T_1844[1].imaginary.node @[DspReal.scala 81:21]
    BBFMultiply_49_1.in2 <= twiddle[0].imaginary.node @[DspReal.scala 82:21]
    wire _T_1928 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_1928 is invalid @[DspReal.scala 83:19]
    _T_1928.node <= BBFMultiply_49_1.out @[DspReal.scala 84:14]
    wire _T_1934 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_1934 is invalid @[DspReal.scala 165:19]
    _T_1934.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_43_1 of BBFSubtract_43 @[DspReal.scala 102:36]
    BBFSubtract_43_1.out is invalid
    BBFSubtract_43_1.in2 is invalid
    BBFSubtract_43_1.in1 is invalid
    BBFSubtract_43_1.in1 <= _T_1934.node @[DspReal.scala 81:21]
    BBFSubtract_43_1.in2 <= _T_1928.node @[DspReal.scala 82:21]
    wire _T_1941 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_1941 is invalid @[DspReal.scala 83:19]
    _T_1941.node <= BBFSubtract_43_1.out @[DspReal.scala 84:14]
    inst BBFAdd_72_1 of BBFAdd_72 @[DspReal.scala 98:36]
    BBFAdd_72_1.out is invalid
    BBFAdd_72_1.in2 is invalid
    BBFAdd_72_1.in1 is invalid
    BBFAdd_72_1.in1 <= _T_1922.node @[DspReal.scala 81:21]
    BBFAdd_72_1.in2 <= _T_1941.node @[DspReal.scala 82:21]
    wire _T_1947 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_1947 is invalid @[DspReal.scala 83:19]
    _T_1947.node <= BBFAdd_72_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_50_1 of BBFMultiply_50 @[DspReal.scala 106:36]
    BBFMultiply_50_1.out is invalid
    BBFMultiply_50_1.in2 is invalid
    BBFMultiply_50_1.in1 is invalid
    BBFMultiply_50_1.in1 <= _T_1844[1].real.node @[DspReal.scala 81:21]
    BBFMultiply_50_1.in2 <= twiddle[0].imaginary.node @[DspReal.scala 82:21]
    wire _T_1953 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_1953 is invalid @[DspReal.scala 83:19]
    _T_1953.node <= BBFMultiply_50_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_51_1 of BBFMultiply_51 @[DspReal.scala 106:36]
    BBFMultiply_51_1.out is invalid
    BBFMultiply_51_1.in2 is invalid
    BBFMultiply_51_1.in1 is invalid
    BBFMultiply_51_1.in1 <= _T_1844[1].imaginary.node @[DspReal.scala 81:21]
    BBFMultiply_51_1.in2 <= twiddle[0].real.node @[DspReal.scala 82:21]
    wire _T_1959 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_1959 is invalid @[DspReal.scala 83:19]
    _T_1959.node <= BBFMultiply_51_1.out @[DspReal.scala 84:14]
    inst BBFAdd_73_1 of BBFAdd_73 @[DspReal.scala 98:36]
    BBFAdd_73_1.out is invalid
    BBFAdd_73_1.in2 is invalid
    BBFAdd_73_1.in1 is invalid
    BBFAdd_73_1.in1 <= _T_1953.node @[DspReal.scala 81:21]
    BBFAdd_73_1.in2 <= _T_1959.node @[DspReal.scala 82:21]
    wire _T_1965 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_1965 is invalid @[DspReal.scala 83:19]
    _T_1965.node <= BBFAdd_73_1.out @[DspReal.scala 84:14]
    wire _T_1981 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_1981 is invalid @[DspComplex.scala 14:22]
    _T_1981.real.node <= _T_1947.node @[DspComplex.scala 15:17]
    _T_1981.imaginary.node <= _T_1965.node @[DspComplex.scala 16:22]
    inst BBFAdd_74_1 of BBFAdd_74 @[DspReal.scala 98:36]
    BBFAdd_74_1.out is invalid
    BBFAdd_74_1.in2 is invalid
    BBFAdd_74_1.in1 is invalid
    BBFAdd_74_1.in1 <= _T_1918.real.node @[DspReal.scala 81:21]
    BBFAdd_74_1.in2 <= _T_1981.real.node @[DspReal.scala 82:21]
    wire _T_1985 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_1985 is invalid @[DspReal.scala 83:19]
    _T_1985.node <= BBFAdd_74_1.out @[DspReal.scala 84:14]
    inst BBFAdd_75_1 of BBFAdd_75 @[DspReal.scala 98:36]
    BBFAdd_75_1.out is invalid
    BBFAdd_75_1.in2 is invalid
    BBFAdd_75_1.in1 is invalid
    BBFAdd_75_1.in1 <= _T_1918.imaginary.node @[DspReal.scala 81:21]
    BBFAdd_75_1.in2 <= _T_1981.imaginary.node @[DspReal.scala 82:21]
    wire _T_1991 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_1991 is invalid @[DspReal.scala 83:19]
    _T_1991.node <= BBFAdd_75_1.out @[DspReal.scala 84:14]
    wire _T_2007 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_2007 is invalid @[DspComplex.scala 14:22]
    _T_2007.real.node <= _T_1985.node @[DspComplex.scala 15:17]
    _T_2007.imaginary.node <= _T_1991.node @[DspComplex.scala 16:22]
    wire _T_2011 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2011 is invalid @[DspReal.scala 165:19]
    _T_2011.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_44_1 of BBFSubtract_44 @[DspReal.scala 102:36]
    BBFSubtract_44_1.out is invalid
    BBFSubtract_44_1.in2 is invalid
    BBFSubtract_44_1.in1 is invalid
    BBFSubtract_44_1.in1 <= _T_2011.node @[DspReal.scala 81:21]
    BBFSubtract_44_1.in2 <= _T_1981.real.node @[DspReal.scala 82:21]
    wire _T_2018 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2018 is invalid @[DspReal.scala 83:19]
    _T_2018.node <= BBFSubtract_44_1.out @[DspReal.scala 84:14]
    wire _T_2024 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2024 is invalid @[DspReal.scala 165:19]
    _T_2024.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_45_1 of BBFSubtract_45 @[DspReal.scala 102:36]
    BBFSubtract_45_1.out is invalid
    BBFSubtract_45_1.in2 is invalid
    BBFSubtract_45_1.in1 is invalid
    BBFSubtract_45_1.in1 <= _T_2024.node @[DspReal.scala 81:21]
    BBFSubtract_45_1.in2 <= _T_1981.imaginary.node @[DspReal.scala 82:21]
    wire _T_2031 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2031 is invalid @[DspReal.scala 83:19]
    _T_2031.node <= BBFSubtract_45_1.out @[DspReal.scala 84:14]
    wire _T_2047 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_2047 is invalid @[DspComplex.scala 14:22]
    _T_2047.real.node <= _T_2018.node @[DspComplex.scala 15:17]
    _T_2047.imaginary.node <= _T_2031.node @[DspComplex.scala 16:22]
    inst BBFAdd_76_1 of BBFAdd_76 @[DspReal.scala 98:36]
    BBFAdd_76_1.out is invalid
    BBFAdd_76_1.in2 is invalid
    BBFAdd_76_1.in1 is invalid
    BBFAdd_76_1.in1 <= _T_1918.real.node @[DspReal.scala 81:21]
    BBFAdd_76_1.in2 <= _T_2047.real.node @[DspReal.scala 82:21]
    wire _T_2051 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2051 is invalid @[DspReal.scala 83:19]
    _T_2051.node <= BBFAdd_76_1.out @[DspReal.scala 84:14]
    inst BBFAdd_77_1 of BBFAdd_77 @[DspReal.scala 98:36]
    BBFAdd_77_1.out is invalid
    BBFAdd_77_1.in2 is invalid
    BBFAdd_77_1.in1 is invalid
    BBFAdd_77_1.in1 <= _T_1918.imaginary.node @[DspReal.scala 81:21]
    BBFAdd_77_1.in2 <= _T_2047.imaginary.node @[DspReal.scala 82:21]
    wire _T_2057 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2057 is invalid @[DspReal.scala 83:19]
    _T_2057.node <= BBFAdd_77_1.out @[DspReal.scala 84:14]
    wire _T_2073 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_2073 is invalid @[DspComplex.scala 14:22]
    _T_2073.real.node <= _T_2051.node @[DspComplex.scala 15:17]
    _T_2073.imaginary.node <= _T_2057.node @[DspComplex.scala 16:22]
    stage_outputs_1_0.imaginary.node <= _T_2007.imaginary.node @[FFT.scala 136:198]
    stage_outputs_1_0.real.node <= _T_2007.real.node @[FFT.scala 136:198]
    stage_outputs_1_1.imaginary.node <= _T_2073.imaginary.node @[FFT.scala 136:198]
    stage_outputs_1_1.real.node <= _T_2073.real.node @[FFT.scala 136:198]
    cmem _T_2088 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_2091 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_2099 = _T_2088[UInt<1>("h00")], clock
      _T_2099.imaginary.node <= stage_outputs_0_3.imaginary.node @[FFTUtilities.scala 172:29]
      _T_2099.real.node <= stage_outputs_0_3.real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_2107 = _T_2088[UInt<1>("h00")], clock
    wire _T_2149 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[2] @[FFT.scala 132:38]
    _T_2149 is invalid @[FFT.scala 132:38]
    _T_2149[0].imaginary.node <= stage_outputs_0_2.imaginary.node @[FFT.scala 132:38]
    _T_2149[0].real.node <= stage_outputs_0_2.real.node @[FFT.scala 132:38]
    _T_2149[1].imaginary.node <= _T_2107.imaginary.node @[FFT.scala 132:38]
    _T_2149[1].real.node <= _T_2107.real.node @[FFT.scala 132:38]
    node _T_2190 = bits(sync_0, 0, 0) @[FFT.scala 132:167]
    wire _T_2192 : UInt<1> @[FFTUtilities.scala 88:21]
    _T_2192 is invalid @[FFTUtilities.scala 88:21]
    node _T_2194 = add(_T_2190, UInt<1>("h00")) @[FFTUtilities.scala 89:20]
    node _T_2195 = tail(_T_2194, 1) @[FFTUtilities.scala 89:20]
    _T_2192 <= _T_2195 @[FFTUtilities.scala 89:11]
    wire _T_2210 : UInt<1> @[FFTUtilities.scala 88:21]
    _T_2210 is invalid @[FFTUtilities.scala 88:21]
    node _T_2212 = add(_T_2190, UInt<1>("h01")) @[FFTUtilities.scala 89:20]
    node _T_2213 = tail(_T_2212, 1) @[FFTUtilities.scala 89:20]
    _T_2210 <= _T_2213 @[FFTUtilities.scala 89:11]
    wire _T_2268 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[2] @[FFTUtilities.scala 87:8]
    _T_2268 is invalid @[FFTUtilities.scala 87:8]
    _T_2268[0].imaginary.node <= _T_2149[_T_2192].imaginary.node @[FFTUtilities.scala 87:8]
    _T_2268[0].real.node <= _T_2149[_T_2192].real.node @[FFTUtilities.scala 87:8]
    _T_2268[1].imaginary.node <= _T_2149[_T_2210].imaginary.node @[FFTUtilities.scala 87:8]
    _T_2268[1].real.node <= _T_2149[_T_2210].real.node @[FFTUtilities.scala 87:8]
    cmem _T_2323 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_2326 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_2334 = _T_2323[UInt<1>("h00")], clock
      _T_2334.imaginary.node <= _T_2268[0].imaginary.node @[FFTUtilities.scala 172:29]
      _T_2334.real.node <= _T_2268[0].real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_2342 = _T_2323[UInt<1>("h00")], clock
    inst BBFMultiply_52_1 of BBFMultiply_52 @[DspReal.scala 106:36]
    BBFMultiply_52_1.out is invalid
    BBFMultiply_52_1.in2 is invalid
    BBFMultiply_52_1.in1 is invalid
    BBFMultiply_52_1.in1 <= _T_2268[1].real.node @[DspReal.scala 81:21]
    BBFMultiply_52_1.in2 <= twiddle[0].real.node @[DspReal.scala 82:21]
    wire _T_2346 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2346 is invalid @[DspReal.scala 83:19]
    _T_2346.node <= BBFMultiply_52_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_53_1 of BBFMultiply_53 @[DspReal.scala 106:36]
    BBFMultiply_53_1.out is invalid
    BBFMultiply_53_1.in2 is invalid
    BBFMultiply_53_1.in1 is invalid
    BBFMultiply_53_1.in1 <= _T_2268[1].imaginary.node @[DspReal.scala 81:21]
    BBFMultiply_53_1.in2 <= twiddle[0].imaginary.node @[DspReal.scala 82:21]
    wire _T_2352 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2352 is invalid @[DspReal.scala 83:19]
    _T_2352.node <= BBFMultiply_53_1.out @[DspReal.scala 84:14]
    wire _T_2358 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2358 is invalid @[DspReal.scala 165:19]
    _T_2358.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_46_1 of BBFSubtract_46 @[DspReal.scala 102:36]
    BBFSubtract_46_1.out is invalid
    BBFSubtract_46_1.in2 is invalid
    BBFSubtract_46_1.in1 is invalid
    BBFSubtract_46_1.in1 <= _T_2358.node @[DspReal.scala 81:21]
    BBFSubtract_46_1.in2 <= _T_2352.node @[DspReal.scala 82:21]
    wire _T_2365 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2365 is invalid @[DspReal.scala 83:19]
    _T_2365.node <= BBFSubtract_46_1.out @[DspReal.scala 84:14]
    inst BBFAdd_78_1 of BBFAdd_78 @[DspReal.scala 98:36]
    BBFAdd_78_1.out is invalid
    BBFAdd_78_1.in2 is invalid
    BBFAdd_78_1.in1 is invalid
    BBFAdd_78_1.in1 <= _T_2346.node @[DspReal.scala 81:21]
    BBFAdd_78_1.in2 <= _T_2365.node @[DspReal.scala 82:21]
    wire _T_2371 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2371 is invalid @[DspReal.scala 83:19]
    _T_2371.node <= BBFAdd_78_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_54_1 of BBFMultiply_54 @[DspReal.scala 106:36]
    BBFMultiply_54_1.out is invalid
    BBFMultiply_54_1.in2 is invalid
    BBFMultiply_54_1.in1 is invalid
    BBFMultiply_54_1.in1 <= _T_2268[1].real.node @[DspReal.scala 81:21]
    BBFMultiply_54_1.in2 <= twiddle[0].imaginary.node @[DspReal.scala 82:21]
    wire _T_2377 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2377 is invalid @[DspReal.scala 83:19]
    _T_2377.node <= BBFMultiply_54_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_55_1 of BBFMultiply_55 @[DspReal.scala 106:36]
    BBFMultiply_55_1.out is invalid
    BBFMultiply_55_1.in2 is invalid
    BBFMultiply_55_1.in1 is invalid
    BBFMultiply_55_1.in1 <= _T_2268[1].imaginary.node @[DspReal.scala 81:21]
    BBFMultiply_55_1.in2 <= twiddle[0].real.node @[DspReal.scala 82:21]
    wire _T_2383 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2383 is invalid @[DspReal.scala 83:19]
    _T_2383.node <= BBFMultiply_55_1.out @[DspReal.scala 84:14]
    inst BBFAdd_79_1 of BBFAdd_79 @[DspReal.scala 98:36]
    BBFAdd_79_1.out is invalid
    BBFAdd_79_1.in2 is invalid
    BBFAdd_79_1.in1 is invalid
    BBFAdd_79_1.in1 <= _T_2377.node @[DspReal.scala 81:21]
    BBFAdd_79_1.in2 <= _T_2383.node @[DspReal.scala 82:21]
    wire _T_2389 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2389 is invalid @[DspReal.scala 83:19]
    _T_2389.node <= BBFAdd_79_1.out @[DspReal.scala 84:14]
    wire _T_2405 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_2405 is invalid @[DspComplex.scala 14:22]
    _T_2405.real.node <= _T_2371.node @[DspComplex.scala 15:17]
    _T_2405.imaginary.node <= _T_2389.node @[DspComplex.scala 16:22]
    inst BBFAdd_80_1 of BBFAdd_80 @[DspReal.scala 98:36]
    BBFAdd_80_1.out is invalid
    BBFAdd_80_1.in2 is invalid
    BBFAdd_80_1.in1 is invalid
    BBFAdd_80_1.in1 <= _T_2342.real.node @[DspReal.scala 81:21]
    BBFAdd_80_1.in2 <= _T_2405.real.node @[DspReal.scala 82:21]
    wire _T_2409 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2409 is invalid @[DspReal.scala 83:19]
    _T_2409.node <= BBFAdd_80_1.out @[DspReal.scala 84:14]
    inst BBFAdd_81_1 of BBFAdd_81 @[DspReal.scala 98:36]
    BBFAdd_81_1.out is invalid
    BBFAdd_81_1.in2 is invalid
    BBFAdd_81_1.in1 is invalid
    BBFAdd_81_1.in1 <= _T_2342.imaginary.node @[DspReal.scala 81:21]
    BBFAdd_81_1.in2 <= _T_2405.imaginary.node @[DspReal.scala 82:21]
    wire _T_2415 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2415 is invalid @[DspReal.scala 83:19]
    _T_2415.node <= BBFAdd_81_1.out @[DspReal.scala 84:14]
    wire _T_2431 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_2431 is invalid @[DspComplex.scala 14:22]
    _T_2431.real.node <= _T_2409.node @[DspComplex.scala 15:17]
    _T_2431.imaginary.node <= _T_2415.node @[DspComplex.scala 16:22]
    wire _T_2435 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2435 is invalid @[DspReal.scala 165:19]
    _T_2435.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_47_1 of BBFSubtract_47 @[DspReal.scala 102:36]
    BBFSubtract_47_1.out is invalid
    BBFSubtract_47_1.in2 is invalid
    BBFSubtract_47_1.in1 is invalid
    BBFSubtract_47_1.in1 <= _T_2435.node @[DspReal.scala 81:21]
    BBFSubtract_47_1.in2 <= _T_2405.real.node @[DspReal.scala 82:21]
    wire _T_2442 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2442 is invalid @[DspReal.scala 83:19]
    _T_2442.node <= BBFSubtract_47_1.out @[DspReal.scala 84:14]
    wire _T_2448 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2448 is invalid @[DspReal.scala 165:19]
    _T_2448.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_48_1 of BBFSubtract_48 @[DspReal.scala 102:36]
    BBFSubtract_48_1.out is invalid
    BBFSubtract_48_1.in2 is invalid
    BBFSubtract_48_1.in1 is invalid
    BBFSubtract_48_1.in1 <= _T_2448.node @[DspReal.scala 81:21]
    BBFSubtract_48_1.in2 <= _T_2405.imaginary.node @[DspReal.scala 82:21]
    wire _T_2455 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2455 is invalid @[DspReal.scala 83:19]
    _T_2455.node <= BBFSubtract_48_1.out @[DspReal.scala 84:14]
    wire _T_2471 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_2471 is invalid @[DspComplex.scala 14:22]
    _T_2471.real.node <= _T_2442.node @[DspComplex.scala 15:17]
    _T_2471.imaginary.node <= _T_2455.node @[DspComplex.scala 16:22]
    inst BBFAdd_82_1 of BBFAdd_82 @[DspReal.scala 98:36]
    BBFAdd_82_1.out is invalid
    BBFAdd_82_1.in2 is invalid
    BBFAdd_82_1.in1 is invalid
    BBFAdd_82_1.in1 <= _T_2342.real.node @[DspReal.scala 81:21]
    BBFAdd_82_1.in2 <= _T_2471.real.node @[DspReal.scala 82:21]
    wire _T_2475 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2475 is invalid @[DspReal.scala 83:19]
    _T_2475.node <= BBFAdd_82_1.out @[DspReal.scala 84:14]
    inst BBFAdd_83_1 of BBFAdd_83 @[DspReal.scala 98:36]
    BBFAdd_83_1.out is invalid
    BBFAdd_83_1.in2 is invalid
    BBFAdd_83_1.in1 is invalid
    BBFAdd_83_1.in1 <= _T_2342.imaginary.node @[DspReal.scala 81:21]
    BBFAdd_83_1.in2 <= _T_2471.imaginary.node @[DspReal.scala 82:21]
    wire _T_2481 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2481 is invalid @[DspReal.scala 83:19]
    _T_2481.node <= BBFAdd_83_1.out @[DspReal.scala 84:14]
    wire _T_2497 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_2497 is invalid @[DspComplex.scala 14:22]
    _T_2497.real.node <= _T_2475.node @[DspComplex.scala 15:17]
    _T_2497.imaginary.node <= _T_2481.node @[DspComplex.scala 16:22]
    stage_outputs_1_2.imaginary.node <= _T_2431.imaginary.node @[FFT.scala 136:198]
    stage_outputs_1_2.real.node <= _T_2431.real.node @[FFT.scala 136:198]
    stage_outputs_1_3.imaginary.node <= _T_2497.imaginary.node @[FFT.scala 136:198]
    stage_outputs_1_3.real.node <= _T_2497.real.node @[FFT.scala 136:198]
    cmem _T_2512 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_2515 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_2523 = _T_2512[UInt<1>("h00")], clock
      _T_2523.imaginary.node <= stage_outputs_0_5.imaginary.node @[FFTUtilities.scala 172:29]
      _T_2523.real.node <= stage_outputs_0_5.real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_2531 = _T_2512[UInt<1>("h00")], clock
    wire _T_2573 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[2] @[FFT.scala 132:38]
    _T_2573 is invalid @[FFT.scala 132:38]
    _T_2573[0].imaginary.node <= stage_outputs_0_4.imaginary.node @[FFT.scala 132:38]
    _T_2573[0].real.node <= stage_outputs_0_4.real.node @[FFT.scala 132:38]
    _T_2573[1].imaginary.node <= _T_2531.imaginary.node @[FFT.scala 132:38]
    _T_2573[1].real.node <= _T_2531.real.node @[FFT.scala 132:38]
    node _T_2614 = bits(sync_0, 0, 0) @[FFT.scala 132:167]
    wire _T_2616 : UInt<1> @[FFTUtilities.scala 88:21]
    _T_2616 is invalid @[FFTUtilities.scala 88:21]
    node _T_2618 = add(_T_2614, UInt<1>("h00")) @[FFTUtilities.scala 89:20]
    node _T_2619 = tail(_T_2618, 1) @[FFTUtilities.scala 89:20]
    _T_2616 <= _T_2619 @[FFTUtilities.scala 89:11]
    wire _T_2634 : UInt<1> @[FFTUtilities.scala 88:21]
    _T_2634 is invalid @[FFTUtilities.scala 88:21]
    node _T_2636 = add(_T_2614, UInt<1>("h01")) @[FFTUtilities.scala 89:20]
    node _T_2637 = tail(_T_2636, 1) @[FFTUtilities.scala 89:20]
    _T_2634 <= _T_2637 @[FFTUtilities.scala 89:11]
    wire _T_2692 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[2] @[FFTUtilities.scala 87:8]
    _T_2692 is invalid @[FFTUtilities.scala 87:8]
    _T_2692[0].imaginary.node <= _T_2573[_T_2616].imaginary.node @[FFTUtilities.scala 87:8]
    _T_2692[0].real.node <= _T_2573[_T_2616].real.node @[FFTUtilities.scala 87:8]
    _T_2692[1].imaginary.node <= _T_2573[_T_2634].imaginary.node @[FFTUtilities.scala 87:8]
    _T_2692[1].real.node <= _T_2573[_T_2634].real.node @[FFTUtilities.scala 87:8]
    cmem _T_2747 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_2750 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_2758 = _T_2747[UInt<1>("h00")], clock
      _T_2758.imaginary.node <= _T_2692[0].imaginary.node @[FFTUtilities.scala 172:29]
      _T_2758.real.node <= _T_2692[0].real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_2766 = _T_2747[UInt<1>("h00")], clock
    inst BBFMultiply_56_1 of BBFMultiply_56 @[DspReal.scala 106:36]
    BBFMultiply_56_1.out is invalid
    BBFMultiply_56_1.in2 is invalid
    BBFMultiply_56_1.in1 is invalid
    BBFMultiply_56_1.in1 <= _T_2692[1].real.node @[DspReal.scala 81:21]
    BBFMultiply_56_1.in2 <= twiddle[0].real.node @[DspReal.scala 82:21]
    wire _T_2770 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2770 is invalid @[DspReal.scala 83:19]
    _T_2770.node <= BBFMultiply_56_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_57_1 of BBFMultiply_57 @[DspReal.scala 106:36]
    BBFMultiply_57_1.out is invalid
    BBFMultiply_57_1.in2 is invalid
    BBFMultiply_57_1.in1 is invalid
    BBFMultiply_57_1.in1 <= _T_2692[1].imaginary.node @[DspReal.scala 81:21]
    BBFMultiply_57_1.in2 <= twiddle[0].imaginary.node @[DspReal.scala 82:21]
    wire _T_2776 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2776 is invalid @[DspReal.scala 83:19]
    _T_2776.node <= BBFMultiply_57_1.out @[DspReal.scala 84:14]
    wire _T_2782 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2782 is invalid @[DspReal.scala 165:19]
    _T_2782.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_49_1 of BBFSubtract_49 @[DspReal.scala 102:36]
    BBFSubtract_49_1.out is invalid
    BBFSubtract_49_1.in2 is invalid
    BBFSubtract_49_1.in1 is invalid
    BBFSubtract_49_1.in1 <= _T_2782.node @[DspReal.scala 81:21]
    BBFSubtract_49_1.in2 <= _T_2776.node @[DspReal.scala 82:21]
    wire _T_2789 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2789 is invalid @[DspReal.scala 83:19]
    _T_2789.node <= BBFSubtract_49_1.out @[DspReal.scala 84:14]
    inst BBFAdd_84_1 of BBFAdd_84 @[DspReal.scala 98:36]
    BBFAdd_84_1.out is invalid
    BBFAdd_84_1.in2 is invalid
    BBFAdd_84_1.in1 is invalid
    BBFAdd_84_1.in1 <= _T_2770.node @[DspReal.scala 81:21]
    BBFAdd_84_1.in2 <= _T_2789.node @[DspReal.scala 82:21]
    wire _T_2795 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2795 is invalid @[DspReal.scala 83:19]
    _T_2795.node <= BBFAdd_84_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_58_1 of BBFMultiply_58 @[DspReal.scala 106:36]
    BBFMultiply_58_1.out is invalid
    BBFMultiply_58_1.in2 is invalid
    BBFMultiply_58_1.in1 is invalid
    BBFMultiply_58_1.in1 <= _T_2692[1].real.node @[DspReal.scala 81:21]
    BBFMultiply_58_1.in2 <= twiddle[0].imaginary.node @[DspReal.scala 82:21]
    wire _T_2801 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2801 is invalid @[DspReal.scala 83:19]
    _T_2801.node <= BBFMultiply_58_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_59_1 of BBFMultiply_59 @[DspReal.scala 106:36]
    BBFMultiply_59_1.out is invalid
    BBFMultiply_59_1.in2 is invalid
    BBFMultiply_59_1.in1 is invalid
    BBFMultiply_59_1.in1 <= _T_2692[1].imaginary.node @[DspReal.scala 81:21]
    BBFMultiply_59_1.in2 <= twiddle[0].real.node @[DspReal.scala 82:21]
    wire _T_2807 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2807 is invalid @[DspReal.scala 83:19]
    _T_2807.node <= BBFMultiply_59_1.out @[DspReal.scala 84:14]
    inst BBFAdd_85_1 of BBFAdd_85 @[DspReal.scala 98:36]
    BBFAdd_85_1.out is invalid
    BBFAdd_85_1.in2 is invalid
    BBFAdd_85_1.in1 is invalid
    BBFAdd_85_1.in1 <= _T_2801.node @[DspReal.scala 81:21]
    BBFAdd_85_1.in2 <= _T_2807.node @[DspReal.scala 82:21]
    wire _T_2813 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2813 is invalid @[DspReal.scala 83:19]
    _T_2813.node <= BBFAdd_85_1.out @[DspReal.scala 84:14]
    wire _T_2829 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_2829 is invalid @[DspComplex.scala 14:22]
    _T_2829.real.node <= _T_2795.node @[DspComplex.scala 15:17]
    _T_2829.imaginary.node <= _T_2813.node @[DspComplex.scala 16:22]
    inst BBFAdd_86_1 of BBFAdd_86 @[DspReal.scala 98:36]
    BBFAdd_86_1.out is invalid
    BBFAdd_86_1.in2 is invalid
    BBFAdd_86_1.in1 is invalid
    BBFAdd_86_1.in1 <= _T_2766.real.node @[DspReal.scala 81:21]
    BBFAdd_86_1.in2 <= _T_2829.real.node @[DspReal.scala 82:21]
    wire _T_2833 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2833 is invalid @[DspReal.scala 83:19]
    _T_2833.node <= BBFAdd_86_1.out @[DspReal.scala 84:14]
    inst BBFAdd_87_1 of BBFAdd_87 @[DspReal.scala 98:36]
    BBFAdd_87_1.out is invalid
    BBFAdd_87_1.in2 is invalid
    BBFAdd_87_1.in1 is invalid
    BBFAdd_87_1.in1 <= _T_2766.imaginary.node @[DspReal.scala 81:21]
    BBFAdd_87_1.in2 <= _T_2829.imaginary.node @[DspReal.scala 82:21]
    wire _T_2839 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2839 is invalid @[DspReal.scala 83:19]
    _T_2839.node <= BBFAdd_87_1.out @[DspReal.scala 84:14]
    wire _T_2855 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_2855 is invalid @[DspComplex.scala 14:22]
    _T_2855.real.node <= _T_2833.node @[DspComplex.scala 15:17]
    _T_2855.imaginary.node <= _T_2839.node @[DspComplex.scala 16:22]
    wire _T_2859 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2859 is invalid @[DspReal.scala 165:19]
    _T_2859.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_50_1 of BBFSubtract_50 @[DspReal.scala 102:36]
    BBFSubtract_50_1.out is invalid
    BBFSubtract_50_1.in2 is invalid
    BBFSubtract_50_1.in1 is invalid
    BBFSubtract_50_1.in1 <= _T_2859.node @[DspReal.scala 81:21]
    BBFSubtract_50_1.in2 <= _T_2829.real.node @[DspReal.scala 82:21]
    wire _T_2866 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2866 is invalid @[DspReal.scala 83:19]
    _T_2866.node <= BBFSubtract_50_1.out @[DspReal.scala 84:14]
    wire _T_2872 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_2872 is invalid @[DspReal.scala 165:19]
    _T_2872.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_51_1 of BBFSubtract_51 @[DspReal.scala 102:36]
    BBFSubtract_51_1.out is invalid
    BBFSubtract_51_1.in2 is invalid
    BBFSubtract_51_1.in1 is invalid
    BBFSubtract_51_1.in1 <= _T_2872.node @[DspReal.scala 81:21]
    BBFSubtract_51_1.in2 <= _T_2829.imaginary.node @[DspReal.scala 82:21]
    wire _T_2879 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2879 is invalid @[DspReal.scala 83:19]
    _T_2879.node <= BBFSubtract_51_1.out @[DspReal.scala 84:14]
    wire _T_2895 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_2895 is invalid @[DspComplex.scala 14:22]
    _T_2895.real.node <= _T_2866.node @[DspComplex.scala 15:17]
    _T_2895.imaginary.node <= _T_2879.node @[DspComplex.scala 16:22]
    inst BBFAdd_88_1 of BBFAdd_88 @[DspReal.scala 98:36]
    BBFAdd_88_1.out is invalid
    BBFAdd_88_1.in2 is invalid
    BBFAdd_88_1.in1 is invalid
    BBFAdd_88_1.in1 <= _T_2766.real.node @[DspReal.scala 81:21]
    BBFAdd_88_1.in2 <= _T_2895.real.node @[DspReal.scala 82:21]
    wire _T_2899 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2899 is invalid @[DspReal.scala 83:19]
    _T_2899.node <= BBFAdd_88_1.out @[DspReal.scala 84:14]
    inst BBFAdd_89_1 of BBFAdd_89 @[DspReal.scala 98:36]
    BBFAdd_89_1.out is invalid
    BBFAdd_89_1.in2 is invalid
    BBFAdd_89_1.in1 is invalid
    BBFAdd_89_1.in1 <= _T_2766.imaginary.node @[DspReal.scala 81:21]
    BBFAdd_89_1.in2 <= _T_2895.imaginary.node @[DspReal.scala 82:21]
    wire _T_2905 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_2905 is invalid @[DspReal.scala 83:19]
    _T_2905.node <= BBFAdd_89_1.out @[DspReal.scala 84:14]
    wire _T_2921 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_2921 is invalid @[DspComplex.scala 14:22]
    _T_2921.real.node <= _T_2899.node @[DspComplex.scala 15:17]
    _T_2921.imaginary.node <= _T_2905.node @[DspComplex.scala 16:22]
    stage_outputs_1_4.imaginary.node <= _T_2855.imaginary.node @[FFT.scala 136:198]
    stage_outputs_1_4.real.node <= _T_2855.real.node @[FFT.scala 136:198]
    stage_outputs_1_5.imaginary.node <= _T_2921.imaginary.node @[FFT.scala 136:198]
    stage_outputs_1_5.real.node <= _T_2921.real.node @[FFT.scala 136:198]
    cmem _T_2936 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_2939 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_2947 = _T_2936[UInt<1>("h00")], clock
      _T_2947.imaginary.node <= stage_outputs_0_7.imaginary.node @[FFTUtilities.scala 172:29]
      _T_2947.real.node <= stage_outputs_0_7.real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_2955 = _T_2936[UInt<1>("h00")], clock
    wire _T_2997 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[2] @[FFT.scala 132:38]
    _T_2997 is invalid @[FFT.scala 132:38]
    _T_2997[0].imaginary.node <= stage_outputs_0_6.imaginary.node @[FFT.scala 132:38]
    _T_2997[0].real.node <= stage_outputs_0_6.real.node @[FFT.scala 132:38]
    _T_2997[1].imaginary.node <= _T_2955.imaginary.node @[FFT.scala 132:38]
    _T_2997[1].real.node <= _T_2955.real.node @[FFT.scala 132:38]
    node _T_3038 = bits(sync_0, 0, 0) @[FFT.scala 132:167]
    wire _T_3040 : UInt<1> @[FFTUtilities.scala 88:21]
    _T_3040 is invalid @[FFTUtilities.scala 88:21]
    node _T_3042 = add(_T_3038, UInt<1>("h00")) @[FFTUtilities.scala 89:20]
    node _T_3043 = tail(_T_3042, 1) @[FFTUtilities.scala 89:20]
    _T_3040 <= _T_3043 @[FFTUtilities.scala 89:11]
    wire _T_3058 : UInt<1> @[FFTUtilities.scala 88:21]
    _T_3058 is invalid @[FFTUtilities.scala 88:21]
    node _T_3060 = add(_T_3038, UInt<1>("h01")) @[FFTUtilities.scala 89:20]
    node _T_3061 = tail(_T_3060, 1) @[FFTUtilities.scala 89:20]
    _T_3058 <= _T_3061 @[FFTUtilities.scala 89:11]
    wire _T_3116 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[2] @[FFTUtilities.scala 87:8]
    _T_3116 is invalid @[FFTUtilities.scala 87:8]
    _T_3116[0].imaginary.node <= _T_2997[_T_3040].imaginary.node @[FFTUtilities.scala 87:8]
    _T_3116[0].real.node <= _T_2997[_T_3040].real.node @[FFTUtilities.scala 87:8]
    _T_3116[1].imaginary.node <= _T_2997[_T_3058].imaginary.node @[FFTUtilities.scala 87:8]
    _T_3116[1].real.node <= _T_2997[_T_3058].real.node @[FFTUtilities.scala 87:8]
    cmem _T_3171 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_3174 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_3182 = _T_3171[UInt<1>("h00")], clock
      _T_3182.imaginary.node <= _T_3116[0].imaginary.node @[FFTUtilities.scala 172:29]
      _T_3182.real.node <= _T_3116[0].real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_3190 = _T_3171[UInt<1>("h00")], clock
    inst BBFMultiply_60_1 of BBFMultiply_60 @[DspReal.scala 106:36]
    BBFMultiply_60_1.out is invalid
    BBFMultiply_60_1.in2 is invalid
    BBFMultiply_60_1.in1 is invalid
    BBFMultiply_60_1.in1 <= _T_3116[1].real.node @[DspReal.scala 81:21]
    BBFMultiply_60_1.in2 <= twiddle[0].real.node @[DspReal.scala 82:21]
    wire _T_3194 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3194 is invalid @[DspReal.scala 83:19]
    _T_3194.node <= BBFMultiply_60_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_61_1 of BBFMultiply_61 @[DspReal.scala 106:36]
    BBFMultiply_61_1.out is invalid
    BBFMultiply_61_1.in2 is invalid
    BBFMultiply_61_1.in1 is invalid
    BBFMultiply_61_1.in1 <= _T_3116[1].imaginary.node @[DspReal.scala 81:21]
    BBFMultiply_61_1.in2 <= twiddle[0].imaginary.node @[DspReal.scala 82:21]
    wire _T_3200 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3200 is invalid @[DspReal.scala 83:19]
    _T_3200.node <= BBFMultiply_61_1.out @[DspReal.scala 84:14]
    wire _T_3206 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_3206 is invalid @[DspReal.scala 165:19]
    _T_3206.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_52_1 of BBFSubtract_52 @[DspReal.scala 102:36]
    BBFSubtract_52_1.out is invalid
    BBFSubtract_52_1.in2 is invalid
    BBFSubtract_52_1.in1 is invalid
    BBFSubtract_52_1.in1 <= _T_3206.node @[DspReal.scala 81:21]
    BBFSubtract_52_1.in2 <= _T_3200.node @[DspReal.scala 82:21]
    wire _T_3213 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3213 is invalid @[DspReal.scala 83:19]
    _T_3213.node <= BBFSubtract_52_1.out @[DspReal.scala 84:14]
    inst BBFAdd_90_1 of BBFAdd_90 @[DspReal.scala 98:36]
    BBFAdd_90_1.out is invalid
    BBFAdd_90_1.in2 is invalid
    BBFAdd_90_1.in1 is invalid
    BBFAdd_90_1.in1 <= _T_3194.node @[DspReal.scala 81:21]
    BBFAdd_90_1.in2 <= _T_3213.node @[DspReal.scala 82:21]
    wire _T_3219 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3219 is invalid @[DspReal.scala 83:19]
    _T_3219.node <= BBFAdd_90_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_62_1 of BBFMultiply_62 @[DspReal.scala 106:36]
    BBFMultiply_62_1.out is invalid
    BBFMultiply_62_1.in2 is invalid
    BBFMultiply_62_1.in1 is invalid
    BBFMultiply_62_1.in1 <= _T_3116[1].real.node @[DspReal.scala 81:21]
    BBFMultiply_62_1.in2 <= twiddle[0].imaginary.node @[DspReal.scala 82:21]
    wire _T_3225 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3225 is invalid @[DspReal.scala 83:19]
    _T_3225.node <= BBFMultiply_62_1.out @[DspReal.scala 84:14]
    inst BBFMultiply_63_1 of BBFMultiply_63 @[DspReal.scala 106:36]
    BBFMultiply_63_1.out is invalid
    BBFMultiply_63_1.in2 is invalid
    BBFMultiply_63_1.in1 is invalid
    BBFMultiply_63_1.in1 <= _T_3116[1].imaginary.node @[DspReal.scala 81:21]
    BBFMultiply_63_1.in2 <= twiddle[0].real.node @[DspReal.scala 82:21]
    wire _T_3231 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3231 is invalid @[DspReal.scala 83:19]
    _T_3231.node <= BBFMultiply_63_1.out @[DspReal.scala 84:14]
    inst BBFAdd_91_1 of BBFAdd_91 @[DspReal.scala 98:36]
    BBFAdd_91_1.out is invalid
    BBFAdd_91_1.in2 is invalid
    BBFAdd_91_1.in1 is invalid
    BBFAdd_91_1.in1 <= _T_3225.node @[DspReal.scala 81:21]
    BBFAdd_91_1.in2 <= _T_3231.node @[DspReal.scala 82:21]
    wire _T_3237 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3237 is invalid @[DspReal.scala 83:19]
    _T_3237.node <= BBFAdd_91_1.out @[DspReal.scala 84:14]
    wire _T_3253 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_3253 is invalid @[DspComplex.scala 14:22]
    _T_3253.real.node <= _T_3219.node @[DspComplex.scala 15:17]
    _T_3253.imaginary.node <= _T_3237.node @[DspComplex.scala 16:22]
    inst BBFAdd_92_1 of BBFAdd_92 @[DspReal.scala 98:36]
    BBFAdd_92_1.out is invalid
    BBFAdd_92_1.in2 is invalid
    BBFAdd_92_1.in1 is invalid
    BBFAdd_92_1.in1 <= _T_3190.real.node @[DspReal.scala 81:21]
    BBFAdd_92_1.in2 <= _T_3253.real.node @[DspReal.scala 82:21]
    wire _T_3257 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3257 is invalid @[DspReal.scala 83:19]
    _T_3257.node <= BBFAdd_92_1.out @[DspReal.scala 84:14]
    inst BBFAdd_93_1 of BBFAdd_93 @[DspReal.scala 98:36]
    BBFAdd_93_1.out is invalid
    BBFAdd_93_1.in2 is invalid
    BBFAdd_93_1.in1 is invalid
    BBFAdd_93_1.in1 <= _T_3190.imaginary.node @[DspReal.scala 81:21]
    BBFAdd_93_1.in2 <= _T_3253.imaginary.node @[DspReal.scala 82:21]
    wire _T_3263 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3263 is invalid @[DspReal.scala 83:19]
    _T_3263.node <= BBFAdd_93_1.out @[DspReal.scala 84:14]
    wire _T_3279 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_3279 is invalid @[DspComplex.scala 14:22]
    _T_3279.real.node <= _T_3257.node @[DspComplex.scala 15:17]
    _T_3279.imaginary.node <= _T_3263.node @[DspComplex.scala 16:22]
    wire _T_3283 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_3283 is invalid @[DspReal.scala 165:19]
    _T_3283.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_53_1 of BBFSubtract_53 @[DspReal.scala 102:36]
    BBFSubtract_53_1.out is invalid
    BBFSubtract_53_1.in2 is invalid
    BBFSubtract_53_1.in1 is invalid
    BBFSubtract_53_1.in1 <= _T_3283.node @[DspReal.scala 81:21]
    BBFSubtract_53_1.in2 <= _T_3253.real.node @[DspReal.scala 82:21]
    wire _T_3290 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3290 is invalid @[DspReal.scala 83:19]
    _T_3290.node <= BBFSubtract_53_1.out @[DspReal.scala 84:14]
    wire _T_3296 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_3296 is invalid @[DspReal.scala 165:19]
    _T_3296.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst BBFSubtract_54_1 of BBFSubtract_54 @[DspReal.scala 102:36]
    BBFSubtract_54_1.out is invalid
    BBFSubtract_54_1.in2 is invalid
    BBFSubtract_54_1.in1 is invalid
    BBFSubtract_54_1.in1 <= _T_3296.node @[DspReal.scala 81:21]
    BBFSubtract_54_1.in2 <= _T_3253.imaginary.node @[DspReal.scala 82:21]
    wire _T_3303 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3303 is invalid @[DspReal.scala 83:19]
    _T_3303.node <= BBFSubtract_54_1.out @[DspReal.scala 84:14]
    wire _T_3319 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_3319 is invalid @[DspComplex.scala 14:22]
    _T_3319.real.node <= _T_3290.node @[DspComplex.scala 15:17]
    _T_3319.imaginary.node <= _T_3303.node @[DspComplex.scala 16:22]
    inst BBFAdd_94_1 of BBFAdd_94 @[DspReal.scala 98:36]
    BBFAdd_94_1.out is invalid
    BBFAdd_94_1.in2 is invalid
    BBFAdd_94_1.in1 is invalid
    BBFAdd_94_1.in1 <= _T_3190.real.node @[DspReal.scala 81:21]
    BBFAdd_94_1.in2 <= _T_3319.real.node @[DspReal.scala 82:21]
    wire _T_3323 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3323 is invalid @[DspReal.scala 83:19]
    _T_3323.node <= BBFAdd_94_1.out @[DspReal.scala 84:14]
    inst BBFAdd_95_1 of BBFAdd_95 @[DspReal.scala 98:36]
    BBFAdd_95_1.out is invalid
    BBFAdd_95_1.in2 is invalid
    BBFAdd_95_1.in1 is invalid
    BBFAdd_95_1.in1 <= _T_3190.imaginary.node @[DspReal.scala 81:21]
    BBFAdd_95_1.in2 <= _T_3319.imaginary.node @[DspReal.scala 82:21]
    wire _T_3329 : {node : UInt<64>} @[DspReal.scala 83:19]
    _T_3329 is invalid @[DspReal.scala 83:19]
    _T_3329.node <= BBFAdd_95_1.out @[DspReal.scala 84:14]
    wire _T_3345 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}} @[DspComplex.scala 14:22]
    _T_3345 is invalid @[DspComplex.scala 14:22]
    _T_3345.real.node <= _T_3323.node @[DspComplex.scala 15:17]
    _T_3345.imaginary.node <= _T_3329.node @[DspComplex.scala 16:22]
    stage_outputs_1_6.imaginary.node <= _T_3279.imaginary.node @[FFT.scala 136:198]
    stage_outputs_1_6.real.node <= _T_3279.real.node @[FFT.scala 136:198]
    stage_outputs_1_7.imaginary.node <= _T_3345.imaginary.node @[FFT.scala 136:198]
    stage_outputs_1_7.real.node <= _T_3345.real.node @[FFT.scala 136:198]
    cmem _T_3360 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_3363 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_3371 = _T_3360[UInt<1>("h00")], clock
      _T_3371.imaginary.node <= stage_outputs_1_1.imaginary.node @[FFTUtilities.scala 172:29]
      _T_3371.real.node <= stage_outputs_1_1.real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_3379 = _T_3360[UInt<1>("h00")], clock
    wire _T_3421 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[2] @[FFT.scala 132:38]
    _T_3421 is invalid @[FFT.scala 132:38]
    _T_3421[0].imaginary.node <= stage_outputs_1_0.imaginary.node @[FFT.scala 132:38]
    _T_3421[0].real.node <= stage_outputs_1_0.real.node @[FFT.scala 132:38]
    _T_3421[1].imaginary.node <= _T_3379.imaginary.node @[FFT.scala 132:38]
    _T_3421[1].real.node <= _T_3379.real.node @[FFT.scala 132:38]
    node _T_3462 = bits(sync_1, 0, 0) @[FFT.scala 132:167]
    wire _T_3464 : UInt<1> @[FFTUtilities.scala 88:21]
    _T_3464 is invalid @[FFTUtilities.scala 88:21]
    node _T_3466 = add(_T_3462, UInt<1>("h00")) @[FFTUtilities.scala 89:20]
    node _T_3467 = tail(_T_3466, 1) @[FFTUtilities.scala 89:20]
    _T_3464 <= _T_3467 @[FFTUtilities.scala 89:11]
    wire _T_3482 : UInt<1> @[FFTUtilities.scala 88:21]
    _T_3482 is invalid @[FFTUtilities.scala 88:21]
    node _T_3484 = add(_T_3462, UInt<1>("h01")) @[FFTUtilities.scala 89:20]
    node _T_3485 = tail(_T_3484, 1) @[FFTUtilities.scala 89:20]
    _T_3482 <= _T_3485 @[FFTUtilities.scala 89:11]
    wire _T_3540 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[2] @[FFTUtilities.scala 87:8]
    _T_3540 is invalid @[FFTUtilities.scala 87:8]
    _T_3540[0].imaginary.node <= _T_3421[_T_3464].imaginary.node @[FFTUtilities.scala 87:8]
    _T_3540[0].real.node <= _T_3421[_T_3464].real.node @[FFTUtilities.scala 87:8]
    _T_3540[1].imaginary.node <= _T_3421[_T_3482].imaginary.node @[FFTUtilities.scala 87:8]
    _T_3540[1].real.node <= _T_3421[_T_3482].real.node @[FFTUtilities.scala 87:8]
    cmem _T_3595 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_3598 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_3606 = _T_3595[UInt<1>("h00")], clock
      _T_3606.imaginary.node <= _T_3540[0].imaginary.node @[FFTUtilities.scala 172:29]
      _T_3606.real.node <= _T_3540[0].real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_3614 = _T_3595[UInt<1>("h00")], clock
    stage_outputs_2_0.imaginary.node <= _T_3614.imaginary.node @[FFT.scala 134:175]
    stage_outputs_2_0.real.node <= _T_3614.real.node @[FFT.scala 134:175]
    stage_outputs_2_1.imaginary.node <= _T_3540[1].imaginary.node @[FFT.scala 134:175]
    stage_outputs_2_1.real.node <= _T_3540[1].real.node @[FFT.scala 134:175]
    cmem _T_3629 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_3632 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_3640 = _T_3629[UInt<1>("h00")], clock
      _T_3640.imaginary.node <= stage_outputs_1_3.imaginary.node @[FFTUtilities.scala 172:29]
      _T_3640.real.node <= stage_outputs_1_3.real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_3648 = _T_3629[UInt<1>("h00")], clock
    wire _T_3690 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[2] @[FFT.scala 132:38]
    _T_3690 is invalid @[FFT.scala 132:38]
    _T_3690[0].imaginary.node <= stage_outputs_1_2.imaginary.node @[FFT.scala 132:38]
    _T_3690[0].real.node <= stage_outputs_1_2.real.node @[FFT.scala 132:38]
    _T_3690[1].imaginary.node <= _T_3648.imaginary.node @[FFT.scala 132:38]
    _T_3690[1].real.node <= _T_3648.real.node @[FFT.scala 132:38]
    node _T_3731 = bits(sync_1, 0, 0) @[FFT.scala 132:167]
    wire _T_3733 : UInt<1> @[FFTUtilities.scala 88:21]
    _T_3733 is invalid @[FFTUtilities.scala 88:21]
    node _T_3735 = add(_T_3731, UInt<1>("h00")) @[FFTUtilities.scala 89:20]
    node _T_3736 = tail(_T_3735, 1) @[FFTUtilities.scala 89:20]
    _T_3733 <= _T_3736 @[FFTUtilities.scala 89:11]
    wire _T_3751 : UInt<1> @[FFTUtilities.scala 88:21]
    _T_3751 is invalid @[FFTUtilities.scala 88:21]
    node _T_3753 = add(_T_3731, UInt<1>("h01")) @[FFTUtilities.scala 89:20]
    node _T_3754 = tail(_T_3753, 1) @[FFTUtilities.scala 89:20]
    _T_3751 <= _T_3754 @[FFTUtilities.scala 89:11]
    wire _T_3809 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[2] @[FFTUtilities.scala 87:8]
    _T_3809 is invalid @[FFTUtilities.scala 87:8]
    _T_3809[0].imaginary.node <= _T_3690[_T_3733].imaginary.node @[FFTUtilities.scala 87:8]
    _T_3809[0].real.node <= _T_3690[_T_3733].real.node @[FFTUtilities.scala 87:8]
    _T_3809[1].imaginary.node <= _T_3690[_T_3751].imaginary.node @[FFTUtilities.scala 87:8]
    _T_3809[1].real.node <= _T_3690[_T_3751].real.node @[FFTUtilities.scala 87:8]
    cmem _T_3864 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_3867 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_3875 = _T_3864[UInt<1>("h00")], clock
      _T_3875.imaginary.node <= _T_3809[0].imaginary.node @[FFTUtilities.scala 172:29]
      _T_3875.real.node <= _T_3809[0].real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_3883 = _T_3864[UInt<1>("h00")], clock
    stage_outputs_2_2.imaginary.node <= _T_3883.imaginary.node @[FFT.scala 134:175]
    stage_outputs_2_2.real.node <= _T_3883.real.node @[FFT.scala 134:175]
    stage_outputs_2_3.imaginary.node <= _T_3809[1].imaginary.node @[FFT.scala 134:175]
    stage_outputs_2_3.real.node <= _T_3809[1].real.node @[FFT.scala 134:175]
    cmem _T_3898 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_3901 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_3909 = _T_3898[UInt<1>("h00")], clock
      _T_3909.imaginary.node <= stage_outputs_1_5.imaginary.node @[FFTUtilities.scala 172:29]
      _T_3909.real.node <= stage_outputs_1_5.real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_3917 = _T_3898[UInt<1>("h00")], clock
    wire _T_3959 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[2] @[FFT.scala 132:38]
    _T_3959 is invalid @[FFT.scala 132:38]
    _T_3959[0].imaginary.node <= stage_outputs_1_4.imaginary.node @[FFT.scala 132:38]
    _T_3959[0].real.node <= stage_outputs_1_4.real.node @[FFT.scala 132:38]
    _T_3959[1].imaginary.node <= _T_3917.imaginary.node @[FFT.scala 132:38]
    _T_3959[1].real.node <= _T_3917.real.node @[FFT.scala 132:38]
    node _T_4000 = bits(sync_1, 0, 0) @[FFT.scala 132:167]
    wire _T_4002 : UInt<1> @[FFTUtilities.scala 88:21]
    _T_4002 is invalid @[FFTUtilities.scala 88:21]
    node _T_4004 = add(_T_4000, UInt<1>("h00")) @[FFTUtilities.scala 89:20]
    node _T_4005 = tail(_T_4004, 1) @[FFTUtilities.scala 89:20]
    _T_4002 <= _T_4005 @[FFTUtilities.scala 89:11]
    wire _T_4020 : UInt<1> @[FFTUtilities.scala 88:21]
    _T_4020 is invalid @[FFTUtilities.scala 88:21]
    node _T_4022 = add(_T_4000, UInt<1>("h01")) @[FFTUtilities.scala 89:20]
    node _T_4023 = tail(_T_4022, 1) @[FFTUtilities.scala 89:20]
    _T_4020 <= _T_4023 @[FFTUtilities.scala 89:11]
    wire _T_4078 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[2] @[FFTUtilities.scala 87:8]
    _T_4078 is invalid @[FFTUtilities.scala 87:8]
    _T_4078[0].imaginary.node <= _T_3959[_T_4002].imaginary.node @[FFTUtilities.scala 87:8]
    _T_4078[0].real.node <= _T_3959[_T_4002].real.node @[FFTUtilities.scala 87:8]
    _T_4078[1].imaginary.node <= _T_3959[_T_4020].imaginary.node @[FFTUtilities.scala 87:8]
    _T_4078[1].real.node <= _T_3959[_T_4020].real.node @[FFTUtilities.scala 87:8]
    cmem _T_4133 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_4136 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_4144 = _T_4133[UInt<1>("h00")], clock
      _T_4144.imaginary.node <= _T_4078[0].imaginary.node @[FFTUtilities.scala 172:29]
      _T_4144.real.node <= _T_4078[0].real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_4152 = _T_4133[UInt<1>("h00")], clock
    stage_outputs_2_4.imaginary.node <= _T_4152.imaginary.node @[FFT.scala 134:175]
    stage_outputs_2_4.real.node <= _T_4152.real.node @[FFT.scala 134:175]
    stage_outputs_2_5.imaginary.node <= _T_4078[1].imaginary.node @[FFT.scala 134:175]
    stage_outputs_2_5.real.node <= _T_4078[1].real.node @[FFT.scala 134:175]
    cmem _T_4167 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_4170 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_4178 = _T_4167[UInt<1>("h00")], clock
      _T_4178.imaginary.node <= stage_outputs_1_7.imaginary.node @[FFTUtilities.scala 172:29]
      _T_4178.real.node <= stage_outputs_1_7.real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_4186 = _T_4167[UInt<1>("h00")], clock
    wire _T_4228 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[2] @[FFT.scala 132:38]
    _T_4228 is invalid @[FFT.scala 132:38]
    _T_4228[0].imaginary.node <= stage_outputs_1_6.imaginary.node @[FFT.scala 132:38]
    _T_4228[0].real.node <= stage_outputs_1_6.real.node @[FFT.scala 132:38]
    _T_4228[1].imaginary.node <= _T_4186.imaginary.node @[FFT.scala 132:38]
    _T_4228[1].real.node <= _T_4186.real.node @[FFT.scala 132:38]
    node _T_4269 = bits(sync_1, 0, 0) @[FFT.scala 132:167]
    wire _T_4271 : UInt<1> @[FFTUtilities.scala 88:21]
    _T_4271 is invalid @[FFTUtilities.scala 88:21]
    node _T_4273 = add(_T_4269, UInt<1>("h00")) @[FFTUtilities.scala 89:20]
    node _T_4274 = tail(_T_4273, 1) @[FFTUtilities.scala 89:20]
    _T_4271 <= _T_4274 @[FFTUtilities.scala 89:11]
    wire _T_4289 : UInt<1> @[FFTUtilities.scala 88:21]
    _T_4289 is invalid @[FFTUtilities.scala 88:21]
    node _T_4291 = add(_T_4269, UInt<1>("h01")) @[FFTUtilities.scala 89:20]
    node _T_4292 = tail(_T_4291, 1) @[FFTUtilities.scala 89:20]
    _T_4289 <= _T_4292 @[FFTUtilities.scala 89:11]
    wire _T_4347 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[2] @[FFTUtilities.scala 87:8]
    _T_4347 is invalid @[FFTUtilities.scala 87:8]
    _T_4347[0].imaginary.node <= _T_4228[_T_4271].imaginary.node @[FFTUtilities.scala 87:8]
    _T_4347[0].real.node <= _T_4228[_T_4271].real.node @[FFTUtilities.scala 87:8]
    _T_4347[1].imaginary.node <= _T_4228[_T_4289].imaginary.node @[FFTUtilities.scala 87:8]
    _T_4347[1].real.node <= _T_4228[_T_4289].real.node @[FFTUtilities.scala 87:8]
    cmem _T_4402 : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[1] @[FFTUtilities.scala 169:21]
    when io.in.valid : @[Counter.scala 59:17]
      skip @[Counter.scala 59:17]
    node _T_4405 = and(io.in.valid, UInt<1>("h01")) @[Counter.scala 60:20]
    when io.in.valid : @[FFTUtilities.scala 171:17]
      infer mport _T_4413 = _T_4402[UInt<1>("h00")], clock
      _T_4413.imaginary.node <= _T_4347[0].imaginary.node @[FFTUtilities.scala 172:29]
      _T_4413.real.node <= _T_4347[0].real.node @[FFTUtilities.scala 172:29]
      skip @[FFTUtilities.scala 171:17]
    infer mport _T_4421 = _T_4402[UInt<1>("h00")], clock
    stage_outputs_2_6.imaginary.node <= _T_4421.imaginary.node @[FFT.scala 134:175]
    stage_outputs_2_6.real.node <= _T_4421.real.node @[FFT.scala 134:175]
    stage_outputs_2_7.imaginary.node <= _T_4347[1].imaginary.node @[FFT.scala 134:175]
    stage_outputs_2_7.real.node <= _T_4347[1].real.node @[FFT.scala 134:175]
    io.out.bits[0].imaginary.node <= stage_outputs_2_0.imaginary.node @[FFT.scala 143:15]
    io.out.bits[0].real.node <= stage_outputs_2_0.real.node @[FFT.scala 143:15]
    io.out.bits[1].imaginary.node <= stage_outputs_2_1.imaginary.node @[FFT.scala 143:15]
    io.out.bits[1].real.node <= stage_outputs_2_1.real.node @[FFT.scala 143:15]
    io.out.bits[2].imaginary.node <= stage_outputs_2_2.imaginary.node @[FFT.scala 143:15]
    io.out.bits[2].real.node <= stage_outputs_2_2.real.node @[FFT.scala 143:15]
    io.out.bits[3].imaginary.node <= stage_outputs_2_3.imaginary.node @[FFT.scala 143:15]
    io.out.bits[3].real.node <= stage_outputs_2_3.real.node @[FFT.scala 143:15]
    io.out.bits[4].imaginary.node <= stage_outputs_2_4.imaginary.node @[FFT.scala 143:15]
    io.out.bits[4].real.node <= stage_outputs_2_4.real.node @[FFT.scala 143:15]
    io.out.bits[5].imaginary.node <= stage_outputs_2_5.imaginary.node @[FFT.scala 143:15]
    io.out.bits[5].real.node <= stage_outputs_2_5.real.node @[FFT.scala 143:15]
    io.out.bits[6].imaginary.node <= stage_outputs_2_6.imaginary.node @[FFT.scala 143:15]
    io.out.bits[6].real.node <= stage_outputs_2_6.real.node @[FFT.scala 143:15]
    io.out.bits[7].imaginary.node <= stage_outputs_2_7.imaginary.node @[FFT.scala 143:15]
    io.out.bits[7].real.node <= stage_outputs_2_7.real.node @[FFT.scala 143:15]
    
  module FFTUnpacked : 
    input clock : Clock
    input reset : UInt<1>
    output io : {flip in : {valid : UInt<1>, bits : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[8], sync : UInt<1>}, out : {valid : UInt<1>, bits : {real : {node : UInt<64>}, imaginary : {node : UInt<64>}}[8], sync : UInt<1>}}
    
    io is invalid
    io is invalid
    wire _T_5 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_5 is invalid @[DspReal.scala 165:19]
    _T_5.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_12 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_12 is invalid @[DspReal.scala 165:19]
    _T_12.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_316 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_316 is invalid @[DspReal.scala 165:19]
    _T_316.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    wire _T_323 : {node : UInt<64>} @[DspReal.scala 165:19]
    _T_323 is invalid @[DspReal.scala 165:19]
    _T_323.node <= UInt<64>("h00") @[DspReal.scala 166:14]
    inst direct of DirectFFT @[FFT.scala 155:22]
    direct.io is invalid
    direct.clock <= clock
    direct.reset <= reset
    io.out.sync <= direct.io.out.sync @[FFT.scala 156:10]
    io.out.bits[0].imaginary.node <= direct.io.out.bits[0].imaginary.node @[FFT.scala 156:10]
    io.out.bits[0].real.node <= direct.io.out.bits[0].real.node @[FFT.scala 156:10]
    io.out.bits[1].imaginary.node <= direct.io.out.bits[1].imaginary.node @[FFT.scala 156:10]
    io.out.bits[1].real.node <= direct.io.out.bits[1].real.node @[FFT.scala 156:10]
    io.out.bits[2].imaginary.node <= direct.io.out.bits[2].imaginary.node @[FFT.scala 156:10]
    io.out.bits[2].real.node <= direct.io.out.bits[2].real.node @[FFT.scala 156:10]
    io.out.bits[3].imaginary.node <= direct.io.out.bits[3].imaginary.node @[FFT.scala 156:10]
    io.out.bits[3].real.node <= direct.io.out.bits[3].real.node @[FFT.scala 156:10]
    io.out.bits[4].imaginary.node <= direct.io.out.bits[4].imaginary.node @[FFT.scala 156:10]
    io.out.bits[4].real.node <= direct.io.out.bits[4].real.node @[FFT.scala 156:10]
    io.out.bits[5].imaginary.node <= direct.io.out.bits[5].imaginary.node @[FFT.scala 156:10]
    io.out.bits[5].real.node <= direct.io.out.bits[5].real.node @[FFT.scala 156:10]
    io.out.bits[6].imaginary.node <= direct.io.out.bits[6].imaginary.node @[FFT.scala 156:10]
    io.out.bits[6].real.node <= direct.io.out.bits[6].real.node @[FFT.scala 156:10]
    io.out.bits[7].imaginary.node <= direct.io.out.bits[7].imaginary.node @[FFT.scala 156:10]
    io.out.bits[7].real.node <= direct.io.out.bits[7].real.node @[FFT.scala 156:10]
    io.out.valid <= direct.io.out.valid @[FFT.scala 156:10]
    inst BiplexFFT_1 of BiplexFFT @[FFT.scala 159:24]
    BiplexFFT_1.io is invalid
    BiplexFFT_1.clock <= clock
    BiplexFFT_1.reset <= reset
    direct.io.in.sync <= BiplexFFT_1.io.out.sync @[FFT.scala 160:18]
    direct.io.in.bits[0].imaginary.node <= BiplexFFT_1.io.out.bits[0].imaginary.node @[FFT.scala 160:18]
    direct.io.in.bits[0].real.node <= BiplexFFT_1.io.out.bits[0].real.node @[FFT.scala 160:18]
    direct.io.in.bits[1].imaginary.node <= BiplexFFT_1.io.out.bits[1].imaginary.node @[FFT.scala 160:18]
    direct.io.in.bits[1].real.node <= BiplexFFT_1.io.out.bits[1].real.node @[FFT.scala 160:18]
    direct.io.in.bits[2].imaginary.node <= BiplexFFT_1.io.out.bits[2].imaginary.node @[FFT.scala 160:18]
    direct.io.in.bits[2].real.node <= BiplexFFT_1.io.out.bits[2].real.node @[FFT.scala 160:18]
    direct.io.in.bits[3].imaginary.node <= BiplexFFT_1.io.out.bits[3].imaginary.node @[FFT.scala 160:18]
    direct.io.in.bits[3].real.node <= BiplexFFT_1.io.out.bits[3].real.node @[FFT.scala 160:18]
    direct.io.in.bits[4].imaginary.node <= BiplexFFT_1.io.out.bits[4].imaginary.node @[FFT.scala 160:18]
    direct.io.in.bits[4].real.node <= BiplexFFT_1.io.out.bits[4].real.node @[FFT.scala 160:18]
    direct.io.in.bits[5].imaginary.node <= BiplexFFT_1.io.out.bits[5].imaginary.node @[FFT.scala 160:18]
    direct.io.in.bits[5].real.node <= BiplexFFT_1.io.out.bits[5].real.node @[FFT.scala 160:18]
    direct.io.in.bits[6].imaginary.node <= BiplexFFT_1.io.out.bits[6].imaginary.node @[FFT.scala 160:18]
    direct.io.in.bits[6].real.node <= BiplexFFT_1.io.out.bits[6].real.node @[FFT.scala 160:18]
    direct.io.in.bits[7].imaginary.node <= BiplexFFT_1.io.out.bits[7].imaginary.node @[FFT.scala 160:18]
    direct.io.in.bits[7].real.node <= BiplexFFT_1.io.out.bits[7].real.node @[FFT.scala 160:18]
    direct.io.in.valid <= BiplexFFT_1.io.out.valid @[FFT.scala 160:18]
    BiplexFFT_1.io.in.sync <= io.in.sync @[FFT.scala 161:18]
    BiplexFFT_1.io.in.bits[0].imaginary.node <= io.in.bits[0].imaginary.node @[FFT.scala 161:18]
    BiplexFFT_1.io.in.bits[0].real.node <= io.in.bits[0].real.node @[FFT.scala 161:18]
    BiplexFFT_1.io.in.bits[1].imaginary.node <= io.in.bits[1].imaginary.node @[FFT.scala 161:18]
    BiplexFFT_1.io.in.bits[1].real.node <= io.in.bits[1].real.node @[FFT.scala 161:18]
    BiplexFFT_1.io.in.bits[2].imaginary.node <= io.in.bits[2].imaginary.node @[FFT.scala 161:18]
    BiplexFFT_1.io.in.bits[2].real.node <= io.in.bits[2].real.node @[FFT.scala 161:18]
    BiplexFFT_1.io.in.bits[3].imaginary.node <= io.in.bits[3].imaginary.node @[FFT.scala 161:18]
    BiplexFFT_1.io.in.bits[3].real.node <= io.in.bits[3].real.node @[FFT.scala 161:18]
    BiplexFFT_1.io.in.bits[4].imaginary.node <= io.in.bits[4].imaginary.node @[FFT.scala 161:18]
    BiplexFFT_1.io.in.bits[4].real.node <= io.in.bits[4].real.node @[FFT.scala 161:18]
    BiplexFFT_1.io.in.bits[5].imaginary.node <= io.in.bits[5].imaginary.node @[FFT.scala 161:18]
    BiplexFFT_1.io.in.bits[5].real.node <= io.in.bits[5].real.node @[FFT.scala 161:18]
    BiplexFFT_1.io.in.bits[6].imaginary.node <= io.in.bits[6].imaginary.node @[FFT.scala 161:18]
    BiplexFFT_1.io.in.bits[6].real.node <= io.in.bits[6].real.node @[FFT.scala 161:18]
    BiplexFFT_1.io.in.bits[7].imaginary.node <= io.in.bits[7].imaginary.node @[FFT.scala 161:18]
    BiplexFFT_1.io.in.bits[7].real.node <= io.in.bits[7].real.node @[FFT.scala 161:18]
    BiplexFFT_1.io.in.valid <= io.in.valid @[FFT.scala 161:18]
    
